[hpsdr] C122_CLK Question On Penny(Lane)

[John Westmoreland]

HPSDR,

Upon examination of the RTL in Quartus-II for C122_CLK for Penny(Lane) - I
don't explicitly see the method in which the 122.88 MHz clk is divided by
10 so that the system clk is
12.288 MHz - can someone point out where this divide by 10 is?  Looking at
the RTL shows the fan-out to be 212 and it is being fed from the pin
directly into the clks for the internal logic on PennyLane.
Note I am looking at version 1.6 of the PnennyLane verilog.

So, unless that clk is being divided prior to the pin on PennyLane -
C122_CLK is running at 122.288 MHz (125 MHz?) internal to the FPGA.  Is the
divide by 10 external to the FPGA?

Another question if it is OK - I see that the AIN1, AIN2, and AIN5 pins on
the ADC are going through 2 D FF's - and the code says to use nCS to latch
that data - is it always latched on every read or do you have to explicitly
toggle the nCS?  I see the ADC state machine seems to to this - but just
wanted to ask what the thinking was on the ADC state machine is that was OK.

73's,
John
AJ6BC
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