[hpsdr] SDR DF

[Phil Harman]

Hi Joe,

Thanks for continuing to work on this problem. I agree that the Atlas bus
is not the correct place for the master CORDIC output.

What about using the LVDS drivers on the Mercury boards?  From memory
these will run at 800Mbps if you clock on both clock edges. I also recall
seeing an Altera Meagafunction that provides parallel to serial to
parallel conversion.

Good luck!

73 Phil...


> Frankly, I'm surprised that I have as yet been unable to solve the startup
> phase problem.  Maybe someone has a new suggestion as to how we might do
> it.  I've considered Phil's latest novel suggestion about perhaps using a
> common CORDIC for all three receivers but that seems to require being able
> to pass the 16-bit ADC values at 122.88 MHz sampling rate from the
> non-master receivers, in parallel, to the master receiver where the common
> CORDIC would reside.  That high-speed data transfer seems to me to be
> problematic to implement and would seem to me to be not possible or
> advisable to do via the Atlas bus even if we decided to commandeer the
> necessary Atlas bus lines to do it.




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