[hpsdr] Functional diagram of 10MHz switching in the Mercury FPGA

[Joe Martin K5SO]

All, 

During recent conversations with Paul VE7KHZ concerning how the 10 MHz reference clock is switched and routed within the Mercury FPGA to lock the 122.88 Mhz VXCO I prepared a functional diagram to show the internal details, including a mapping of the relevant variables of the Verilog firmware design to the diagram.  These particular details are not available by simply examining the Mercury schematic diagram.

http://www.k5so.com/Mercury_10MHz_clock_switching.jpg

Perhaps the functional diagram might be of use to you if you are unclear as to what is done with the various 10 MHz clock inputs that exist for Mercury.  

The internal scheme used in Mercury is similarly used in Hermes and Angelia (different FPGA pin numbers, of course, since Hermes/Angelia use different variants of FPGA and there is no Atlas bus in those two cases).  

73,  Joe K5SO