[hpsdr] Mercury + Metis: more Bandwidth possible?

[Achim Vollhardt]

Hi all,
I am wondering if there is a possibility to increase the overall
bandwidth given the Metis Gigabit (well, 100 Mbit/s) interface.

Looking at the Mercury block diagram, the FPGA downsamples/decimates to
around 250 ksps, but even when assuming 24 bit I/Q samples this results
in 12Mbit/s. How much more can be squeezed out, I think at least a
factor 4-6 more should be possible.. did anybody try this yet? I guess
the FPGA firmware needs some tweaks though..

Thanks and best regards,
Achim