[hpsdr] Bringing up Penny

[georg Prinz]

Hello,

I installed the FPGA and tested it successfully with Quartus Programmer 
and PennyTestImage.sof via Altera USB Blaster.

After installing EPSC4 I am stuck to load it with PennyTestImage.pof.  I 
am able to attach EPSC4 as Flash Device. But the programmer does not 
accept PennyTestImage. pof neither in JFTAG mode nor in Active Serial 
Programming.

One other test on the FPGA I couldn't do, is the check on IO pins with 
scope, LEDs etc. according to item 10 in the a.m. procedure. How can I 
switch on this test?

73, Georg, dl2kp


Am 10.02.2014 22:46, schrieb Scott Cowling:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Hi Georg,
>
> Use P3 to load the FPGA via JTAG.
>
> The PennyTestImage.sof file is available here:
> http://openhpsdr.org/support/Penelope/PennyTestImage.sof
>
> 73,
> Scotty WA2DFI
>
> At 22:03 2014-02-10 +0100, Georg Prinz wrote:
>> ***** High Performance Software Defined Radio Discussion List *****
>>
>> Hello,
>>
>> after long time I decided to bring up my second Penny. My guideline is
>> is a pamphlet with 22 points to be followed taken out of the archive
>> called "Bringing up Penny".
>>
>> Item 7 says: fit P4 JTAG header
>>
>> Item 9: Load FPGA via JTAG with PennyTestImage.sof
>>
>> Unfortunately there is no P4 on the board to be installed.
>>
>> Could anybody tell me how to load the FPGA without P4? Does any other
>> procedure exist?
>>
>> Where can I find the
>> PennyTestImage.sof file?
>>
>> Or does an onother guide exist to bring up the board.
>>
>> 73, Georg, dl2kp
>>
>>
>>
>>
>>
>>
>>
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>
>
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