[hpsdr] EER Support in PowerSDR and Hermes
phil at pharman.org
Wed Jun 18 05:29:18 PDT 2014
Some of you have already noticed that in the latest version of PowerSDR there is a DSP setting called ‘EER’.
This is development code for some of our members who are experimenting with Envelope Elimination and Restoration (EER) power amplifiers. And by ‘power’ I mean lots of power! EER power amplifiers can reach very high efficiencies and hence require very little in the way of cooling. The phrase ‘pocket kilowatt’ is perhaps not too much of an exaggeration!
This technique requires the envelope of the signal to be detected, which is used to amplitude modulate the PA stage, plus a phase modulated carrier to drive the PA RF transistor or FET.
I’ve had a long standing interest in EER amplifiers and we do have an openHPSDR project - Thor – see
which has been stagnant for some time.
In the past if, for example, an SSB signal was being processed for use with an EER amplifier then the envelope would be detected and used to control a PWM power supply. The output of the power supply is then used to amplitude modulate the PA. The phase modulated carrier would be generated by clipping the SSB signal.
In order to remove the PWM switching frequency from the output of the power supply a LPF is required. This filter introduces at time delay between the resulting envelope signal and the phase modulated RF signal. This delay severely degrades the overall performance of the EER PA. To overcome this some form of compensating delay is needed and in the past this has been provided using an analogue delay line.
There is also quite a lot of analogue processing of the SSB signal required e.g. envelope detector, level shifting, PWM ramp generation and a comparator.
It seemed to me that all of this analogue processing could be done digitally in the FPGA and the low level drive signal required by the PWM provided directly from an FPGA pin.
Well it turns out its not quite as easy as that but we were on the right track. With much assistance from Warren, NR0V, we have been able to successfully provide both the RF and PWM drive signal for an EER amplifier fully digitally. One of the major breakthroughs was Warrens idea of how to user PowerSDR to provide the compensating delay between the RF carrier and envelope.
When processing SSB conventionally in PowerSDR the data from the PC to the SDR Hardware consists of Left and Right audio plus the I & Q signals that will be interpolated to the required RF frequency.
In EER mode, rather than sending Left and Right audio, Warren sends the same I & Q data twice but with an adjustable time delay ( in 0.01us steps) between the two sets of I & Q data. In the FPGA the I & Q samples are converted into the envelope signal and then passed to a Pulse Width Modulator running at 240kHz.
This PWM signal is output on a spare FPGA pin on the Hermes board. By adjusting the delay setting in PowerSDR the inherent delay in the post PWM filter can be exactly compensated.
The clipped SSB signal is provided by the conventional I&Q signals, although some EER amplifiers are driven with unclipped RF.
Whilst generating a accurate envelope and RF signal is important there are still many other items to consider. However, just like with our conventional linear amplifiers applying PureSignal to an EER PA appears to have the same benefits.
We are still in the experimental phase but early results look very encouraging.
Another application for this technology is to greatly improve the efficiency of a conventional linear amplifier by using the envelope signal to vary the supply voltage to the PA stage. This technique is call ‘Envelope Tracking’ and is used by modern cell phones to reduce battery consumption. More information about this technique in a future update.
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