[hpsdr] CW Latency

[Phil Harman]

I’ve been experimenting with moving the CW generation (sidetone and RF) from the PC to the FPGA.  This eliminates the trip to and from the PC when using CW and hence reduces latency.

So far the results have been very encouraging with no delay from pressing the key until sidetone and RF is available.  Required delays for the RF, to prevent ‘hot switching’ of PA and linear relays, does not add any latency to the sidetone. 

I’ve been able to implement variable sidetone frequency and level plus shaping of the leading and trailing edges of sidetone and RF.

During development we did make one change to PowerSDR that will reduce the latency of the RF from PowerSDR which will improve CW performance irrespective of using PC or the FPGA for CW generation.

There are some changes to PowerSDR in order to support this and we then need to do some Beta testing which will require some gun CW operators!

In which case I expect  it will be a few weeks before this is publically available. 

At the moment it is not intended to include an Iambic keyer in the FPGA, mainly due to the myriad of options/features such keyers offer.  So an external Iambic keyer, or straight key,  will be required.  

73 Phil...VK6PH 

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