[hpsdr] WG: Hermes doesn't come to life

[Christian Hauswurz]

  Hi Bob,

thanks for your reply. All clocks are feeding into the FPGA properly except for the main 122.8 MHz clock. 
I measured the frequency and level from the main oscillator until it feeds into the ADC. Before it enters the ADC all seems pretty normal but the clock signal between the ADC and the FPGA looks distorted and is presumably to low. 
I re-soldered all pins on the ADC but it's still the same error. Looks like i have to order a new one. :-/ 
Are you able to measure the clock frequency between the ADC and FPGA and tell me what the signal should look like on a functioning device?


Best regards
Chris DL3HC




   
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