[hpsdr] Fwd: Hpsdr Digest, Vol 204, Issue 2

ad0es ad0es at ad0es.net
Fri Apr 14 12:32:13 PDT 2023


Hi.

Phil Harmon VK6PH was the lead:

Video presentation <https://www.youtube.com/watch?v=Ob4o8vrC4yM>

If you look in the archives you can find entries in the 2018 timeframe.

Something totally hosed my website link, it should be:

https://ad0es.net/dfcADC/



On 4/14/23 1:14 PM, Bob Stricklin wrote:
> Hi Steve,
>
> I sent a reply via HPSDR but got a notice it was being held for some 
> reason so sending direct.
>
> Bob N5BRG
>
>> Begin forwarded message:
>>
>> *From: *Bob Stricklin <bstrick at n5brg.com>
>> *Subject: **Re: Hpsdr Digest, Vol 204, Issue 2*
>> *Date: *April 14, 2023 at 7:46:15 AM CDT
>> *To: *hpsdr at lists.openhpsdr.org
>>
>> Steve,
>>
>> I do not recall what the goal of Minerva was going to be? This is not 
>> on the list of HPSDR projects that I see. Can you update me/us on 
>> this or post a URL to a description?
>>
>> For the RF consider adding a connector to a PCB and use the 
>> Cariiboulite-6G-01 from Crowd Supply. This is an RF capable board 
>> that can work up to 6 GHz which normally plugs onto a RPi. It should 
>> work with other processor bases.
>> The advantage is the board is available at a modest cost, it is built 
>> and tested, an FPGA is included so it is possible to customize the 
>> verily for many applications. The design is open source and the chips 
>> are apparently available.
>>
>> You may also do a similar thing with an RTL-SDR but not have the 
>> level of flexibility the Cariboulite would offer.
>>
>> Bob
>>
>>> ----------------------------------------------------------------------
>>>
>>> Message: 1
>>> Date: Thu, 13 Apr 2023 12:54:26 -0600
>>> From: ad0es <ad0es at ad0es.net>
>>> To: hpsdr at lists.openhpsdr.org
>>> Subject: [hpsdr] Phoenix
>>> Message-ID: <fab64982-a775-1cd5-2cf0-64ad5a593e94 at ad0es.net>
>>> Content-Type: text/plain; charset="utf-8"; Format="flowed"
>>>
>>> Hi all,
>>>
>>> I am in the final stages of prototyping a receive only version of
>>> Minerva. The PCIe/FPGA/ADC parts
>>> are working. The final step is the design of an RF appropriate front
>>> end. I'm afraid this is outside
>>> of my skill set...
>>>
>>> I would like the community's help in this design.? Any
>>> comments/suggestions/criticisms are welcome!
>>> I've put together a website with info and sample schematics:
>>>
>>> The website 
>>> <https://url.emailprotection.link/?bfl3Wn4SkzMeF9dpnddV7H2vEGHr9gP4nAOU4pT4IZd7GYKsjyYvjfZKiSbpUzVFpW-u-8OlGy0UMQp5gW3cptA~~>
>>>
>>> 73,
>>> Steve AD0ES
>>>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.openhpsdr.org/pipermail/hpsdr-openhpsdr.org/attachments/20230414/a2fc9548/attachment.htm>


More information about the Hpsdr mailing list