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<DIV>Phil, this may not be significant / or an issue, however,<BR>I have been reviewing your latest schematic and my eyes are telling me that:</DIV>
<DIV> </DIV>
<DIV>Cyress USB chip nets:</DIV>
<DIV> </DIV>
<DIV>FX2_T1 pin 30<BR>FX2_T2 pin 31<BR>FX2_PC6 pin 78<BR>FX2_PC7 pin 79 &<BR>FX2_INT5 pin 106 are all unused (& probably correct so).</DIV>
<DIV> </DIV>
<DIV>Cyclone II EP2C5-208 nets:</DIV>
<DIV> </DIV>
<DIV>FPGA_DATA0 pin 20<BR>FPGA_DCLK pin 21 &<BR>FPGA_NCEO are unused (& probably correct)</DIV>
<DIV> </DIV>
<DIV>I also think pin 118 (currently assigned ATLAS_X17C1) should be assigned ATLAS_NRESET.<BR>Thats assuming the USB reset is usually from the FPGA & not the Atlas bus. </DIV>
<DIV>Great work I really don't know how you guys can be so productive?</DIV>
<DIV> </DIV>
<DIV>The provisional layout looks great!</DIV>
<DIV> </DIV>
<DIV>Kevin<BR>M0KHZ</DIV>
<DIV> </DIV>
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