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That's what I'm trying to say: I think you need to have some analog
circuitry after the fractional N divider, otherwise you will have
spurs. Be it a PLL, a D/A (see next paragraph), or some sort of magical
low pass filters, it's fundamental to the nature of the beast. If the
LO is going to be driven directly by the fractional N, there is no way
digitally to remove those spurs. The clocked output of a fractional N
can only switch on transitions of the reference, not at exactly the
time required to generate the desired frequency. Thus the output will
have jitter whose peak value will be plus or minus half the reference
clock.<br>
<br>
One option that I have considered, but not even tried to model, is to
use a low resolution D/A at the output of a home made DDS (FPGA). I'd
arrange the D/A to behave as if there were a high gain amplifier after
a conventional DDS, driving the output into saturation except during
the zero transition. Thus the D/A output would be a solid logical one
or zero output except during the transition, during which the output
voltage would be proportional to the remainder in the accumulator (a
clipped sine wave). In other words: the D/A would use the remainder
portion of the DDS accumulator only, and be saturated otherwise. The
D/A output would then be low pass filtered, then sent to a comparator.
The idea being to increase the speed of the zero transition, and to
improve its resolution, since in a digital system the transition timing
is all that's important. A QSD doesn't need a sine wave, but a good
square wave. Hopefully that would reduce some of the spurs and other
noise.<br>
<br>
That's just an idea, but I have decided not to pursue it and don't know
if it has any merit. I've realized that for what I'm trying to
accomplish, I'd be far better of just using a couple crystals.<br>
<br>
Later,<br>
Artie Lekstutis<br>
KC2MFS<br>
<br>
<blockquote
cite="midd3c938ee0606171349m6e316393x3ebd1f89b0adb6f0@mail.gmail.com"
type="cite">Artie, fractional spurs may be compensated by noise
shaping in case of a phase-lock loop. The higher the order delta sigma
modulators, the more the fractional spur energy (quantization noise) is
moved from the phase-lock loop band towards a higher frequency.
<br>
<br>
Assume that there is no phase-lock loop in Bob´s Horton LO idea: There
is just a stable crystal clock which is divided by a fractional-N,
where the output is fed to a QSD for mixing. Would it still be possible
to noise shape in order to compensate for the fractional spurs ?
<br>
<br>
Guido.<br>
<br>
<div><span class="gmail_quote">On 6/17/06, <b
class="gmail_sendername">Arthur J. Lekstutis</b> <<a
href="mailto:Artie@lekstutis.com">Artie@lekstutis.com</a>> wrote:</span>
<blockquote class="gmail_quote"
style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">*****
High Performance Software Defined Radio Discussion List *****<br>
<br>
Hi,<br>
<br>
I can't keep up with you guys as I'm too busy with other projects at the<br>
moment, so I mostly lurk on this list. Perhaps I misunderstand or
missed
<br>
an email some place.<br>
<br>
Wouldn't a purely digital "fractional N" divider generate significant<br>
spurs? The duration of any digital signal from a synchronous device<br>
must, by definition, be multiples of the clock cycle. Trying to get
<br>
around this with a fractional N divider will result in uncertainty of<br>
the desired output of approximately the clock period. The jitter would<br>
equal the clock period, the magnitude would depend on the current<br>
fraction. I would expect spurs from that. Or am I missing something?
<br>
<br>
Adding a random number generator to a fractional N divider to choice<br>
when to switch from one frequency to another (which is what I think a<br>
fractional N divider basically does) might spread out the spurs out,
but
<br>
they'll still be there.<br>
<br>
I think you need to be happy with an integer divider, or introduce an<br>
analog PLL, if you want to minimize noise.<br>
<br>
Back to lurking....<br>
<br>
Later,<br>
Artie Lekstutis<br>
KC2MFS<br>
<br>
<br>
>***** High Performance Software Defined Radio Discussion List *****<br>
><br>
>Guido:<br>
><br>
>Doing all of this fractional stuff digitally and never having to
convert<br>
>back to analog is a big win, a huge win. The facts are the
fractional
<br>
>N, without having to go back to analog, but retaining an all digital<br>
>character is a huge win since we remove tons of nastiness due to<br>
>attempting to produce analog waveforms. Our ULTIMATE resolution
should
<br>
>by a 2^16 word size and in this case that is 2.5 kHz. It is going
to be<br>
>a big win.<br>
><br>
>Bob<br>
><br>
><br>
><br>
<br>
<br>
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