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<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>I’d like to pose a question to the FPGA/Verilog gurus
on the list.<o:p></o:p></span></font></p>
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font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>The simplified block diagram found at the following URL
illustrates the current Janus/OZY architecture as I understand it with regards
to the connectivity between the analog inputs and outputs and the USB I/O:
<a href="http://wb6tpu.googlepages.com/janusozysimplifiedblockdiagram">http://wb6tpu.googlepages.com/janusozysimplifiedblockdiagram</a><o:p></o:p></span></font></p>
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font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Noting that there is an FPGA on both the Janus and the OZY
boards, I am wondering if it is practical to do away with one of them if the
equivalent analog to USB connections were to be integrated on the <st1:City
w:st="on"><st1:place w:st="on">Phoenix</st1:place></st1:City> board. Please see
the simplified block diagram at the following URL that illustrates what I am
thinking of: <a
href="http://wb6tpu.googlepages.com/proposedphoenixintegrateblockdiagram">http://wb6tpu.googlepages.com/proposedphoenixintegrateblockdiagram</a><o:p></o:p></span></font></p>
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font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>73s de Ray WB6TPU<o:p></o:p></span></font></p>
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font-family:Arial'><o:p> </o:p></span></font></p>
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font-family:Arial'> </span></font><font color="#999999"><span
style='color:#999999'><o:p></o:p></span></font></p>
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