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<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>Ray,<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>I’ll try to answer and then the
experts can jump all over me.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>Your Janus/Ozy architecture is almost
right, but the PWD lines are in the wrong direction; they actually are from the
Cyclone II FPGA on the Ozy board to the Janus board. What they are for, as I
understand it, is to take the processed I/Q data being returned from the PC and
convert it to analog for the output earphone amplifier of the TLV320AIC23B
CODEC on the Janus board. The Max II CPLD on the Janus board is doing nothing
much at the moment besides cross-connecting Atlas bus signals to internal Janus
signals. It’s the Cyclone II FPGA on the Ozy board that receives the
24-bit I/Q digital data and turns it into PWM data on the Atlas bus; I don’t
think it’s filtered here, so it is analog in timing but digital in
amplitude. That signal is then routed through the Max II CPLD on Janus to be
filtered to AM and fed to the amplifier on the Janus board. So in your drawing,
the PWM arrow points the other way and the signals go through the EPM240.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>Anyway, given that you can squeeze in all
on a board, the <st1:City w:st="on"><st1:place w:st="on">Phoenix</st1:place></st1:City>
architecture is fine, again with the PWM arrow reversed and connected to the
FPGA. These are not physically small chips, and there are a _<i><span
style='font-style:italic'>lot</span></i>_ of traces.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'>Let the stone throwing begin.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'> Chris
– AE6VK<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
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<hr size=2 width="100%" align=center tabindex=-1>
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<p class=MsoNormal><b><font size=2 face=Tahoma><span style='font-size:10.0pt;
font-family:Tahoma;font-weight:bold'>From:</span></font></b><font size=2
face=Tahoma><span style='font-size:10.0pt;font-family:Tahoma'> Ray Anderson
[mailto:ray.anderson@xilinx.com] <br>
<b><span style='font-weight:bold'>Sent:</span></b> Wednesday, August 02, 2006
12:02 PM<br>
<b><span style='font-weight:bold'>To:</span></b> hpsdr@hpsdr.org<br>
<b><span style='font-weight:bold'>Subject:</span></b> [hpsdr] Question on
Janus/OZY function integration</span></font><o:p></o:p></p>
</div>
<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>I’d like to pose a question to the FPGA/Verilog gurus
on the list.<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>The simplified block diagram found at the following URL
illustrates the current Janus/OZY architecture as I understand it with regards to
the connectivity between the analog inputs and outputs and the USB I/O:
<a href="http://wb6tpu.googlepages.com/janusozysimplifiedblockdiagram">http://wb6tpu.googlepages.com/janusozysimplifiedblockdiagram</a><o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Noting that there is an FPGA on both the Janus and the OZY
boards, I am wondering if it is practical to do away with one of them if the
equivalent analog to USB connections were to be integrated on the <st1:place
w:st="on"><st1:City w:st="on">Phoenix</st1:City></st1:place> board. Please see
the simplified block diagram at the following URL that illustrates what I am
thinking of: <a
href="http://wb6tpu.googlepages.com/proposedphoenixintegrateblockdiagram">http://wb6tpu.googlepages.com/proposedphoenixintegrateblockdiagram</a><o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>73s de Ray WB6TPU<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><o:p> </o:p></span></font></p>
<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'> </span></font><font color="#999999"><span
style='color:#999999'><o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'><o:p> </o:p></span></font></p>
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