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<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'>I think it may take a software genius who also understands
the hardware/Verilog to decompose the hardware and Verilog block
diagrams into functional "flows". In the DSP world, the
"flow" is generally a simple interrupt, but I think something could
be done. One thing that would help and, I think, should be a
"requirement" is a "media paper" like Phil and Bill wrote
for JANUS. <o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'>
see <a href="http://hpsdr.org/wiki/images/4/46/Janus-DCC-2006-paper.pdf"
title=Janus-DCC-2006-paper.pdf>Media:Janus-DCC-2006-paper.pdf</a> <o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'> <o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'>In my limited experience, DSP and Verilog designers tend to
document their code using comments embedded in the code. This is good for
them but the rest of us may be used to a different paradigm. OK, I used
all the big words I know. 73<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'> <o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'>Tom, N4WBS<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'>Huntsville AL<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=1 face=Tahoma><span style='font-size:9.0pt;
font-family:Tahoma'>HPSDR, TAPR, Norcal QRP, NoGA QRP, NADXC<o:p></o:p></span></font></p>
<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'><o:p> </o:p></span></font></p>
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