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Hi Jason,<BR>
<BR>
Reply in your text below!<BR>
<BR>
73's Phil...VK6APH <BR>
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So am I right in understanding that:<BR>
<BR>
OzyV2-JanusV2 - Code for Ozy that includes code for interacting with<BR>
Janus - must be loaded each time the board is powered up.<BR>
<BR>
Correct! This is done using initozy.bat At the moment this is called manually but could be called within PowerSDR automatically if Janus/Ozy is selected as the sound card.<BR>
<BR>
<BR>
Janus-CPLDV2 - Code for Janus that is loaded once.<BR>
<BR>
Correct! The production boards are pre-programmed with this code. If you build your own board then you need a way of loading this into the CPLD. This can be done in a number of ways<BR>
<BR>
1. A low cost parallel port JTAG programmer<BR>
2. A USB Byte Blaster - either a genuine Altera or clone<BR>
3. Load code into the FX2 to simulate a Byte Blaster<BR>
<BR>
The latter is the most desirable since using that we can access the JTAG chain on the Atlas bus and program the CLPD on the Janus board (or any other future device).<BR>
<BR>
There is GPLed code to do this (can't remember the reference ) available but it needs porting to the Ozy board. I may have found a volunteer to do this at Dayton - if not will call for a volunteer. <BR>
<BR>
We can also program the FPGA flash boot EEPROMs this way that for example will be used on the Penelope and Mercury boards. <BR>
<BR>
If so I guess my big question is should I start planning on a<BR>
Byteblaster to program my Janus with or is there a way that it can be<BR>
done through Ozys USB connection?<BR>
<BR>
See above<BR>
<BR>
<BR>
<span style="color: red;"></span>One other thing I'm still unclear on. In the Ozy block diagram I do<BR>
see a boot flash memory that appears to be for the FPGA....looking at<BR>
the schematic I think this is the 24c128 if I'm reading them right<BR>
(hard to say though since my printouts are so small!)<BR>
<BR>
The 24C128 holds the VID and PID for the USB function of the FX2 chip.<BR>
<BR>
The FPGA can be set to boot from its EPCS4 flash memory but since we are changing the Ozy code quite often for now we have chosen the load the FPGA using initozy.bat each before you start PowerSDR for the first time each session. <a href="parse.pl?redirect=http%3A%2F%2Flists.hpsdr.org%2Fpipermail%2Fhpsdr-hpsdr.org%2F" target="_blank"><span style="color: red;"></span></a><BR>
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