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<DIV><FONT face=Arial size=2><SPAN class=684252220-13082007>______I have an idea
that I want to try out that requires a DDS with a very low phase noise. I
was looking at AD9954, which performs best with a 1x frequency source. I
am sure that I have seen this come up before, but did not pay much attention to
it.</SPAN></FONT></DIV>
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class=684252220-13082007></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=684252220-13082007>Does anyone have a
recommendation for a very low phase noise oscillator for this chip and a place
that I can get it from?</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=684252220-13082007></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=684252220-13082007>- Dan,
N7VE_______</SPAN></FONT></DIV>
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<DIV><FONT face=Arial size=2><SPAN class=684252220-13082007>You might look at
the idea of picking the relevant harmonic of say a 100MHz osc and amplifying and
filtering with one of the Murata 3 or 4 chamber PMR filters. This approach
was used by both G4HGT and G4DDK UHF/SHF transverters and recently by
I0CCG in his AD9951 DDS implementation. The transverter osillators used Butlers
with discreet componets while the I0CCG one used a canned
clock.</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=684252220-13082007></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=684252220-13082007>Someone might
comment on how much cleaner this approach might be compared to an active
multipier or PLL??</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=684252220-13082007></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2><SPAN class=684252220-13082007>Shel
CT1IZU</SPAN></FONT></DIV>
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