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Hi,<br>
<br>
I am new to this group and am interested in SDR. I am a Verilog
FPGA/ASIC design engineer by trade and as such I would like to look at
the code. I saw some example code on the internet and noticed that it
should be written differently when describing RTL code. Don't mean to
step on anyones toes..<span class="moz-smiley-s1"><span> :-) </span></span>
I do think this is a great project. I have a lot of FPGA development
tools and experience as a Verilog design/verification engineer and
would like to see if there is a way to help.<br>
<br>
Kirk Weedman<br>
KD7IRS<br>
<br>
Warren C. Pratt wrote:
<blockquote cite="mid:982C334A96F54CABBB7DD94164822BFB@pcwpratt0"
type="cite">
<pre wrap="">***** High Performance Software Defined Radio Discussion List *****
</pre>
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<div><font face="Arial" size="2"><span class="218444815-12112008">I
have noted the link to the Penelope FPGA code. Am I correct that I
need to install an SVN source management tool to download the code?</span></font></div>
<div><font face="Arial" size="2"><span class="218444815-12112008"></span></font> </div>
<div><font face="Arial" size="2"><span class="218444815-12112008">Thanks,</span></font></div>
<div><font face="Arial" size="2"><span class="218444815-12112008"></span></font> </div>
<div><font face="Arial" size="2"><span class="218444815-12112008">Warren
NR0V</span></font></div>
<div><font face="Arial" size="2"><span class="218444815-12112008"></span></font> </div>
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