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<DIV><FONT face="Times New Roman" size=3>All,<BR><BR>Background:<BR><BR>When
Phil, N8VB, designed the Atlas bus he had the foresight to include <BR>a JTAG
chain. The idea was that in the future (i.e. now!) we will need <BR>to
update the code in the various FPGAs/CPLDs/Flash memory on the <BR>boards that
comprise HPSDR.<BR><BR>We have been very fortunate that the code that TAPR
installed in Janus <BR>and Penelope during manufacture has been relatively
stable and we have not needed to <BR>update any code to date.<BR><BR>This is
about to change since we have a number of active developers <BR>working on the
Mercury FPGA code and I'd like to take advantage of the <BR>ideas and features
they have added as soon as possible.<BR><BR>Beta Testing:<BR><BR>I propose that
we do the Mercury upgrade in 3 stages.<BR><BR>Stage 1: For experienced
users who have the necessary skills and <BR>equipment to quickly beta test the
new code.<BR><BR>Stage 2: For intrepid experimenters who are willing to
install the new <BR>Mercury code that has been validated in Stage 1. No hardware
tools will <BR>be required but some software will need to be installed and
configured <BR>on your PC.<BR><BR>Stage 3: For everyone else. Either an
automatic code upload or a <BR>"click here" application.<BR><BR>For Stage 1 beta
testers I've added a directory called Mercury V2 in SVN here<BR><BR><FONT
face=Arial size=2>< svn://206.216.146.154/svn/repos_sdr_hpsdr/trunk/Mercury
V2 </FONT><BR><BR>Load the Mercury.pof file into the EPCS16 and give us
feedback. </FONT></DIV>
<DIV><FONT face="Times New Roman" size=3>Also load the latest PowerSDR that
supports the new features developed</FONT></DIV>
<DIV><FONT face="Times New Roman" size=3>by Bill, KD5TFD, using SVN from
</FONT></DIV>
<DIV><FONT face="Times New Roman" size=3></FONT> </DIV>
<DIV><FONT face="Times New Roman" size=3><
svn://206.216.146.154/svn/repos_sdr_windows/PowerSDR/branches/kd5tfd/PennyMerge/bin/Release
></FONT></DIV>
<DIV><FONT face="Times New Roman" size=3></FONT> </DIV>
<DIV><FONT face="Times New Roman" size=3>Existing Mercury users may also want to
use this latest version of PowerSDR - in this case just leave the
sampling</FONT></DIV>
<DIV><FONT face="Times New Roman" size=3>rate at 192kHz for now. </FONT></DIV>
<DIV><FONT face="Times New Roman" size=3></FONT> </DIV>
<DIV><FONT face="Times New Roman" size=3>The new code has been contributed
by Darrell Harmon, Cathy Moore, Gerd <BR>DJ8AY, Bill KD5TFD and Alex
VE3NEA. If you, like me, are learning Verilog then have <BR>a look at
Alex's code - simply brilliant.<BR><BR>If you are a suitable Stage 1 beta test
candidate then you are not going to need <BR>any further
instructions.<BR><BR>The new features include:<BR><BR>- selectable sample rates
of 48/96/192kHz<BR>- removal of the roll off at the edges of the bandscope<BR>-
removal of the need to DC correct the DSP chain output<BR>- >100dB of alias
signal rejection outside the bandscope passband<BR>- smaller, faster code<BR>-
improvement to the order dependence of HPSDR cards on the Atlas
bus<BR><BR><BR>For Stage 2 we are going to provide code that loads into the Ozy
board <BR>that makes it simulate an Altera USBBlaster. Using a free
command line <BR>program you will be able to load the required code into the
Mercury <BR>EPCS16 flash memory. Some software will need to be installed on your
PC <BR>and you will need to follow step-by-step instructions. More details
<BR>regarding Step 2 later.<BR><BR>For Stage 3 we hope to fully automate the
process such that the updated <BR>code is automatically loaded when starting an
application or PowerSDR.<BR><BR>Over to the Stage 1 beta testers!<BR><BR>73's
Phil... VK6APH</FONT><BR></DIV></FONT></BODY></HTML>