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<DIV><FONT size=4>Hello Mike, et all,</FONT></DIV>
<DIV><FONT size=4>Audio was excellent. Unfortunately I was not able to get
it real time. So far I've understood everything presented.
</FONT></DIV>
<DIV><FONT size=4>Just want to let you know that I appreciate what you're
doing.</FONT></DIV>
<DIV><FONT size=4>The pace of the lecture seemed just a bit fast, but that may
be because I'm not used to being in school lately. The advantage of being
able to get the lecture in non real time is that I can pause it I need
to.</FONT></DIV>
<DIV><FONT size=4></FONT> </DIV>
<DIV><FONT size=4>The mouse cursor was visible, and again the audio was good
quality.</FONT></DIV>
<DIV><FONT size=4></FONT> </DIV>
<DIV><FONT size=4>My objective in learning VHDL is to possibly synthesize a TTL
project into one Verilog chip. That would be really cool (if I could
actually do it). Hopefully I learn enough to get started on that
project.</FONT></DIV>
<DIV><FONT size=4></FONT> </DIV>
<DIV><FONT size=4>Looking forward to getting the simulator and doing the
labs. I'm a white rabbit, I'm way behind.</FONT></DIV>
<DIV><FONT size=4></FONT> </DIV>
<DIV><FONT size=4>73, Bill, wf4r</FONT></DIV></BODY></HTML>