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<DIV><FONT color=#000000 size=2 face=Arial>Hi Alberto,</FONT></DIV>
<DIV><FONT color=#000000 size=2 face=Arial></FONT> </DIV>
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<DIV><BR>My questions are :<BR><BR>1) Is that true ? In other words, are the
ADC, DAC and FPGA clocks in the Mercury card all phase locked together ?</DIV>
<DIV> </DIV>
<DIV><FONT color=#000000 size=2 face=Arial>Yes, all the clocks are derived
from the master 122.88MHz clock</FONT><BR><BR>2) If 1) is true, how should I
behave when e.g. the input data have a sampling frequency of 96 kHz ?
Should I send<BR> an output frame every two input frames, or
should I send the output frames at the same rates of the input ones,<BR>
repeating the data if need be ?</DIV>
<DIV> </DIV>
<DIV><FONT color=#000000 size=2 face=Arial>Always send the data at 48kHz, just
discard data at higher rates. </FONT><BR><BR>Thanks<BR><BR>73
Alberto i2PHD<BR> </BIG><BR></DIV></FONT></FONT>
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