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Phil Harman wrote:
<blockquote
cite="mid:1284.203.59.8.178.1250558102.squirrel@webmail.eftel.com"
type="cite">
<pre wrap="">Dave is quite correct, given the bursty nature of PC processing we have
implemented large FIFOs in the FPGA code to account for this.
</pre>
</blockquote>
Hi Phil and Dave,<br>
<br>
thanks for the answers. But there is still something that puzzles me.<br>
I am quite familiar with FIFO and Ring buffers, I use them extensively
both in Winrad<br>
and in the new code to interface the HPSDR HW.<br>
<br>
But you need a timing to start a new signal processing cycle on the
PC... when data are coming <br>
from a sound card, that timing is given by the card interrupts, that
happen at a regular<br>
rate, given by the sampling frequency.<br>
<br>
In the case of HPSDR, the only timing available is given by the arrival
of a new USB buffer,<br>
FIFO and Ring buffers can compensate for delays in obtaining CPU cycles
from the <br>
Windows scheduler, but cannot correct the timing.<br>
<br>
And the inherent timing of the HPSDR HW is that of providing 63
samples. Suppose you want<br>
to start a processing cycle that process a 512-sample buffer. How can
you obtain the right<br>
trigger to start it from the HPSDR timing ? 63 has no powers of two in
its prime decomposition,<br>
being it 3 * 3 * 7. So to have a timing without jitter you would need
to fill a buffer of 63 * 512 samples,<br>
and only when it is full you could start a processing cycle being
certain of having no jitter.<br>
<br>
But that size is way too large, it would introduce unacceptable latency.<br>
If you do a close inspection at the process, you see that initially, to
fill a 512 sample buffer, you need<br>
9 buffers of 63 samples, and you remain with (63 - 8) = 55 samples as
'reservoir'.<br>
So for the second 512 sample buffer you need now only 8 buffers of 63
samples, using 8 samples<br>
taken from the 'reservoir'. And so on for some cycles. But then, when
the 'reservoir' is empty,<br>
you need again 9 buffers of 63 samples....<br>
<br>
So the rate of preparation of the 512 sample buffers, which ultimately
is the rate that determines <br>
the timing of the signal processing cycle on the PC, is slightly
uneven, with some jitter. It alternates<br>
between 9 and 8 USB-interrupts (not the right word, but you understand
what I mean).<br>
And frankly I cannot understand how this jitter can be eliminated with
the use of FIFO and/or Ring buffers...<br>
<br>
As said in my previous message, there are absolutely no consequences on
voice/music or CW<br>
signals. My fear is that those few data modes that require phase
coherence can be affected...<br>
<br>
Sorry if I make you spending some time reading this...<br>
<br>
73 Alberto I2PHD<br>
<br>
<br>
<br>
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