<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div>Gerd,<br><br>RRR, okay,very good! I apologize that I misunderstood your problem and bombarded you with such detail, but, on the other hand, I'm very glad to hear that you have the diversity program up and running okay.<br><br>I think Kirk Weedman (<a href="mailto:kirk@hdlexpress.com">kirk@hdlexpress.com</a>) might be the Verilog programmer you need help from (perhaps?). If not, Phil VK6APH can certainly direct you to the appropriate person.<br><br>Good luck with that new clock frequency project!<br><br>73, Joe K5SO<br><br></div><div><div>On Oct 11, 2010, at 1:45 PM, Gerd Loch wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Joe,<br><br>there is a misunderstanding:<br>I need to modify the FPGA code for the different clock frequency 196.608 MHz<br>and have to change clock division factors, decimation factors and<br>accumulator width.<br>I have no problem with the "normal" clock 122.28 MHz and have diversity<br>running. So I need some help from the guy that wrote the FPGA coding.<br>I already got a message who is the one and probably will get help.<br><br>Nevertheless thanks for your support.<br><br>73, Gerd<br>DJ8AY<br><br><br><br></div></blockquote></div><br></body></html>