<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><br></div><div>PowerSDR v1.19.3.1.diversity15 (K5SO 17DEC2010) is available for download at </div><div><br></div><div><a href="http://www.k5so.com/HPSDR_downloads.html">http://www.k5so.com/HPSDR_downloads.html</a></div><div><br></div><div>This version: </div><div><br></div><div>1) adds ADC OVERLOAD alert/warning functionality for the second Mercury board, and </div><div><br></div><div>2) modifies the Diversity Control, re-arranging the control positions, cleaning up the display, and correcting a problem that previously occurred during re-sizing of the Diversity Control window. </div><div><br></div><div>Signal input overload conditions to either Mercury board are now detected and are reported to the PC program, causing the usual "ADC Overload" message to appear on the front panel display and additional warning indications to appear on the appropriate Mercury selection buttons for whichever Mercury board happens to be experiencing input overload conditions. </div><div><br></div><div>As it was necessary to make use of a previously unused Atlas bus line (A4) to implement this additional functionality, it was necessary to modify both Mercury and Ozy FPGA coding, as well as modifying the PC program. </div><div><br></div><div>Mercury v6.3 must be loaded into both Mercury boards. </div><div><br></div><div><div>Mercury v6.3 may be loaded into your Mercury boards via the usual "Program-Mercury-EPCS16.bat" file contained in the nRx_USB_Blaster_binaries folder on the website. The .bat file has been modified to include a selection choice for Mercury v6.3, of course. </div></div><div><br></div><div>Further, a new version of Ozy FPGA code, Ozy v6.1, is automatically loaded via initOzy11.bat when PowerSDR v1.19.3.1.diversity15 is run from a fresh power up of the HPSDR board set, or whenever initOzy11.bat is run even if the board set has not been freshly powered up. This action is transparent to the user. </div><div><br></div><div>For those interested, all Verilog source code and Quartus II project files for these FPGA code mods are available for download from the website. </div><div><br></div><div>As always, I am interested to hear of your experiences, good or bad, with this new diversity program. Thanks to all for helping me to discover any bugs! </div><div><br></div><div>73, Joe K5SO</div><div><br></div><div><br></div></body></html>