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<DIV>Phil/all:</DIV>
<DIV>You might want to check out the James Ahlstrom DDC/DUC board, and his
Quisk. While he has not implemented an iambic keyer in the FPGA, he does
create the transmit CW carrier within the FPGA, which gets around the latency
issue. His board has the advantage of driving the AD9744 reference in pin
with an eight-bit D/A, driven by the FPGA. I think both the Penny boards
and Hermes can also change the AD9744 reference in using a PWM signal generated
by the FPGA, as an ALC signal. Either this can be used, or the FPGA can
use a counter going into the cordic as the “modulation” signal, creating a DC
ramp?? The amount the counter is incremented could be varied by the
CW speed, controlling the ramp angle?</DIV>
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<DIV><FONT face=Arial></FONT> </DIV>
<DIV><FONT face=Arial>Or, am I confused?</FONT></DIV>
<DIV><FONT face=Arial>Terry, WB4JFI</FONT></DIV>
<DIV><FONT face=Arial></FONT> </DIV>
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<DIV style="font-color: black"><B>From:</B> <A title=phil@pharman.org
href="mailto:phil@pharman.org">Phil Harman</A> </DIV>
<DIV><B>Sent:</B> Saturday, April 07, 2012 11:22 PM</DIV>
<DIV><B>To:</B> <A title=boris.njegic@gmail.com
href="mailto:boris.njegic@gmail.com">Boris Njegic</A> ; <A
title=hpsdr@lists.openhpsdr.org
href="mailto:hpsdr@lists.openhpsdr.org">hpsdr@lists.openhpsdr.org</A> </DIV>
<DIV><B>Subject:</B> Re: [hpsdr] Iambic Keyer in Verilog</DIV></DIV></DIV>
<DIV> </DIV></DIV>
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High Performance Software Defined Radio Discussion List *****<BR><BR>
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<DIV>Hi Boris,</DIV>
<DIV> </DIV>
<DIV>Short answer - Yes!</DIV>
<DIV> </DIV>
<DIV>Long answer â Itâs not quite that simple.</DIV>
<DIV> </DIV>
<DIV>If we implement an iambic CW keyer in the FPGA then we will need to also
implement the entire carrier generation. In which case we will need to add a
raised cosine profile, with adjustable timing for different speeds, to the
leading and trailing edges of the CW signal.</DIV>
<DIV> </DIV>
<DIV>The Tx CW offset will also need to be adjustable to suit the operators
preference. In addition the side tone volume will need adjusting as well
as its frequency to suite preferences. It will also require a profile, which may
be different to the RF one, so there are no âclicksâ in the side tone
signal. All these settings will need to be adjusted via additional Command
and Control signals over the Atlas bus. </DIV>
<DIV> </DIV>
<DIV>All of this can be done for sure. But it is so much easier to write this in
a high level language on the PC. </DIV>
<DIV> </DIV>
<DIV>With careful setting of the various buffers in PowerSDR, and using Metis
instead of Ozy, then my gun CW operator friends tell me that latency
is not really an issue. </DIV>
<DIV> </DIV>
<DIV>73 Phil... VK6APH </DIV>
<DIV> </DIV>
<DIV> </DIV>
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<DIV style="font-color: black"><B>From:</B> <A title=boris.njegic@gmail.com
href="mailto:boris.njegic@gmail.com">Boris Njegic</A> </DIV>
<DIV><B>Sent:</B> Sunday, April 08, 2012 4:21 AM</DIV>
<DIV><B>To:</B> <A title=hpsdr@lists.openhpsdr.org
href="mailto:hpsdr@lists.openhpsdr.org">hpsdr@lists.openhpsdr.org</A> </DIV>
<DIV><B>Subject:</B> [hpsdr] Iambic Keyer in Verilog</DIV></DIV></DIV>
<DIV> </DIV></DIV>
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High Performance Software Defined Radio Discussion List *****<BR><BR>
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Hi all,<BR>
<DIV>I am not familiar with Verilog butà is it possible to implement Iambic
keyer like this in Metis? Would that resolve latency problem with CW? Ã </DIV>
<DIV> </DIV>
<DIV>Regards,<BR clear=all>
<DIV>Boris</DIV>
<DIV>9A5ATY</DIV>-- <BR>BNJ<BR></DIV>
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