<html><body><span style="font-family:Verdana; color:#000000; font-size:10pt;"><div>This can be a symptom if one or more of the FPGAs did not meet timing closure during a build. I haven't looked at the builds but someone should check the report files. What can happen is the FPGA may have a few (or many) timing closure errors that are small and don't tend to be a problem when the FPGA is "cool", but as the FPGA heats up they become a problem and this can happen. There should be no timing errors or you run the risk of this happening.</div><div><br></div><div>Kirk Weedman</div><div>KD7IRS<br></div>
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-------- Original Message --------<br>
Subject: Re: [hpsdr] Locking up<br>
From: "Keith" <<a href="mailto:n3ick@cox.net">n3ick@cox.net</a>><br>
Date: Fri, May 25, 2012 1:54 pm<br>
To: "'Hermann'" <<a href="mailto:hvh.net@gmail.com">hvh.net@gmail.com</a>>, "'Bob'" <<a href="mailto:ve3gkm@3web.com">ve3gkm@3web.com</a>>,<br>
<<a href="mailto:hpsdr@lists.openhpsdr.org">hpsdr@lists.openhpsdr.org</a>><br>
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I've seen the same thing happening with PSDR 2.2.3 since I updated to Metis<br>
1.8, Mercury 3.2, Pennylane 1.7, takes over an hour to show up. Cycling the<br>
Start button of PSDR returns a message to check that HPSDR is turned on,<br>
cycling power to the radio and things return to normal. Looked at the event<br>
logs and nothing out of the ordinary was reported there.<br>
<br>
73,<br>
Keith<br>
<br>
-----Original Message-----<br>
From: <a href="mailto:hpsdr-bounces@lists.openhpsdr.org">hpsdr-bounces@lists.openhpsdr.org</a><br>
[<a href="mailto:hpsdr-bounces@lists.openhpsdr.org">mailto:hpsdr-bounces@lists.openhpsdr.org</a>] On Behalf Of Hermann<br>
Sent: Friday, May 25, 2012 12:02 PM<br>
To: Bob; <a href="mailto:hpsdr@lists.openhpsdr.org">hpsdr@lists.openhpsdr.org</a><br>
Subject: Re: [hpsdr] Locking up<br>
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