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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal>Who should be notified of Angelia hardware issues?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>My new 100D would wander in and out of lock no matter what 10MHz level was applied externally. It turns out the problem is the Exteral Clock input PNP diff pair was producing only 0-2V logic output, and with poor risetime, so the slope going thru 1.5V is really slow. Paralleing the 51 ohm emitter resistor with 100 ohms brought the output up to 0-3V, but the risetime, while better is still far slower than the 10MHz clock module, when it is connected. Now it drops out of lock at -10dBm in, but my concern os that the risetime only improves by 2:1 with drive of +10dBm – so it’s still a marginal condition. There appears to be substantial capacitive loading on the output clock line, which begs for a totem-pole driver after the diff pait, rather than the 150 ohm resistive source provided by the diff pair. Who is the keeper of the integrity of the Angelia design?<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>__________________<o:p></o:p></p><p class=MsoNormal>Clyde Washburn, K2UE<o:p></o:p></p><p class=MsoNormal><a href="mailto:k2ue@rochester.rr.com">k2ue@rochester.rr.com</a><o:p></o:p></p><p class=MsoNormal>82 Lasalle Pkwy<o:p></o:p></p><p class=MsoNormal>Victor, NY 14564-9610<o:p></o:p></p><p class=MsoNormal>585-317-7006<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p></div></body></html>