<div dir="ltr"><div>Hi Phil</div><div><br></div>On Sat, Sep 21, 2013 at 11:21 PM, Phil Harman <span dir="ltr"><<a href="mailto:phil@pharman.org" target="_blank">phil@pharman.org</a>></span> wrote:<br><div class="gmail_extra">
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<div><span style="font-size:10pt">I’d
estimate about 5 mins work + compile time.</span><br></div>
<div></div></div></div></div></blockquote><div><br></div><div>Sounds easy, I should be done in about a month then :)</div><div><br></div><div>I think this line needs to be replaced with something that casts 18 bit samples from CIC to 24 bit out_data_I2/Q2 and may be double the decimation rate in filter "B"</div>
<div><br></div><div>firX8R8 fir2 (clock, decimB_avail, decimB_real, decimB_imag, out_strobe, out_data_I2, out_data_Q2);<br></div><div><br></div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<div dir="ltr"><div dir="ltr"><div style="font-size:10pt;font-family:Arial">
<div>My personal preference is to send raw ADC samples to the PC, or a dedicated
single board computer (SBC), and do ALL the processing there <img style="border-style:none" alt="Smile" src="cid:3ADB98B88C2749BAB26A214170EA3781@ShackPC">.</div>
<div></div></div></div></div></blockquote><div><br></div><div> I wonder if the FPGA can do real time data compression so that all data fits into 1 Gbit. I guess about 3x-4x compression ratio would be needed at close too 300 MB/s rate. Or is there a better way?</div>
<div><br></div><div>Hope you are feeling better!</div><div><br></div><div>73</div><div>Vasiliy </div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
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<div><b>From:</b> <a title="gokoyev+k3it@gmail.com" href="mailto:gokoyev+k3it@gmail.com" target="_blank">k3it</a> </div>
<div><b>Sent:</b> Sunday, September 22, 2013 10:32 AM</div>
<div><b>To:</b> <a title="hpsdr@lists.openhpsdr.org" href="mailto:hpsdr@lists.openhpsdr.org" target="_blank">HPSDR list</a> </div>
<div><b>Subject:</b> [hpsdr] filtering options in FPGA</div></div></div>
<div> </div></div>
<div style="font-style:normal;font-size:small;display:inline;text-decoration:none;font-family:Calibri;font-weight:normal"><div>*****
High Performance Software Defined Radio Discussion List *****<br><br>
</div><p>
</p><hr><div><div>
<div dir="ltr">Does anybody know how big of an effort would be to modify the
current Hermes firmware to send the RX streams after the CIC filters and exclude
all FIR processing? I'd like to run an experiment with implementing
a decimating FIR filter on the PC.
<div> </div>
<div>For example I'd like CIC decimate to 384k in FPGA and then CFIR decimate by
4 on the PC to get 96k finished spectrum. is there anything wrong with
this approach?</div>
<div> </div>
<div>I want to do this for two reasons <br></div>
<div>- get feet wet with Verilog </div>
<div>- see how much FPGA space can be recovered by moving part of the processing
to the PC</div>
<div> </div>
<div>-- </div>
<div>73! Vasiliy K3IT</div></div>
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</p><hr>
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