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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>All,</DIV></DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>A
new version of Hermes FPGA code V2.7 is available from here:</DIV></DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'> </DIV></DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'><A
title=http://openhpsdr.org/download.php
href="http://openhpsdr.org/download.php">http://openhpsdr.org/download.php</A></DIV></DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'> </DIV></DIV>
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<DIV
style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>This
fixes a bug where the receive frequency was in error by approximately 1/2
Hz. Thanks to Mike, KF4BQ, for locating this, his explanation follows this
email.</DIV></DIV>
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style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'> </DIV></DIV>
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<DIV
style='FONT-SIZE: small; TEXT-DECORATION: none; FONT-FAMILY: "Calibri"; FONT-WEIGHT: normal; COLOR: #000000; FONT-STYLE: normal; DISPLAY: inline'>Please
note that this update is for Hermes using Alex boards only. Apache Labs will
release an updated version for ANAN radios shortly.</DIV></DIV>
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<DIV>73 Phil...VK6PH </DIV>
<DIV> </DIV>
<DIV> </DIV><FONT face="Times New Roman">I was playing with the FPGA code
and noticed a few things:<BR>1) each 1Hz step is about d35 steps of the
C122_sync_phase_word<BR>2) when using Powersdr I noticed that almost all freqs
seemed to be off <BR>about 1/2Hz high; compared to phase lock sig gen.<BR>3)
verified this 1/2 Hz error using instantiated logic analyzer in <BR>Quartus, and
comparing calc values<BR>example: at 10Mhz the hand calc phase word should be
d349525333.3<BR>the program calcs d349525333 and adds M3 resulting in d349525350
(1/2 Hz <BR>error now).<BR>1Hz up or down is a 35D change in value.<BR><BR>Looks
like a change was made in the last versions of the code adding M3
<BR>(d1172812403). This ends up adding about d17 steps to the
<BR>C122_sync_phase_word. The code was introduced to help since the freq <BR>was
always rounded down. The M3 value should actually be 1000000h = <BR>d16777216
which would fix this error of always rounding down.<BR><BR>With the M3 value
changed: I see the calculated sync_phase_word is <BR>properly rounded. This
effectively added 1/2 step to the <BR>sync_phase_word (not 1/2 Hz) for the
truncation step.<BR><BR>I have changed the M3 value and can see this is a huge
difference in the <BR>orig FPGA code calc. The freq is now selected within 1/35
Hz (maybe <BR>1/70 with new M3 value). The phase display is now very hard to see
move <BR>!! Probably good enough for direct FMT measurements with this
change.<BR><BR>Hope the FPGA team can change the M3 value in the next release.
(change <BR>from d1172812403 to d16777216 in Hermes.v ).<BR><BR>I was going to
made more improvements, but this change is about all that <BR>is
needed.<BR><BR>73, Mike Collins KF4BQ</FONT></DIV></DIV>
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