<html><head><meta http-equiv="content-type" content="text/html; charset=utf-8"></head><body dir="auto"><div>On the red pitaya forum there is a discussion on using external clock for the adc. According to this it could be implemented with the relocation of two zero ohm resistors on the board.</div><div>I also thinking on using red pitaya for sdr, but only for transmitter linearization and experimenting class-e and class-f switching mode pa and techniques like outphasing, which requires two rf output combined with cartesian feedback linearization.<br><br></div><div>Jani, ha5ft</div><div><br>2015. dec. 18. dátummal, 2:38 időpontban Terry Fox <<a href="mailto:tfox@knology.net">tfox@knology.net</a>> írta:<br><br></div><blockquote type="cite"><div><span>***** High Performance Software Defined Radio Discussion List *****</span><br><span></span><br></div></blockquote><blockquote type="cite"><div>
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<div>Thank you for your concerns Graham. Laying out what is expected is
always a good thing!</div>
<div>I would welcome others to check out the RP. I’ve been playing with
one for over six months now, and am still impressed with the cost vs abilities
as an SDR. It’s not a Hermes-killer, but I don’t expect it to be.</div>
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<div>As regards to point 2, it already has Nyquist filters that unfortunately
limit the RP to about 50MHz (I’ve checked). I would like to bypass them
for subsampling.</div>
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<div>Pavel is handling the 125 MHz vs 122.88 MHz by resampling. He was
going to try the CIC filter up/down resampling, I don’t know what the latest
is. I’m more of the opinion that the oscillator should be changed out, but
doing that may be beyond some amateur’s abilities.</div>
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<div>I believe it is an eight-layer board. This thing was designed by some
smart guys playing with particle accelerators. I don’t really buy into the
“lab instrument” usage, due to the rather poor software (so far) and lack of
front-end attenuators/amplifiers.</div>
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<div>As Helmut pointed out, the RP is also supported for the HPSDR version of
PowerSDR.</div>
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<div>How does the HiQSDR, SDR-IQ, and Hermes-Lite fit into the competitive
receiver-exciter domain? If they are “acceptable”, I think the RP is
pretty close to them. (I’m really asking to get a better feel for where it
should fit in the SDR world. I don’t intend to be frivolous)</div>
<div>73, Terry, N4TLF </div>
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<div style="font-color: black"><b>From:</b> <a title="ke9h.graham@gmail.com" href="mailto:ke9h.graham@gmail.com">Graham / KE9H</a> </div>
<div><b>Sent:</b> Thursday, December 17, 2015 7:18 PM</div>
<div><b>To:</b> <a title="dc6ny@gmx.de" href="mailto:dc6ny@gmx.de">Helmut</a>
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<div><b>Cc:</b> <a title="tfox@knology.net" href="mailto:tfox@knology.net">Terry
Fox</a> ; <a title="hpsdr@lists.openhpsdr.org" href="mailto:hpsdr@lists.openhpsdr.org">HPSDR</a> </div>
<div><b>Subject:</b> Re: [hpsdr] FW: SBC Inforce 6410</div></div></div>
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<div>I agree that the Red Pitaya is a great price for a flexible piece of test
equipment.<br></div>
<div>And it might be a great starting point for a low cost transceiver, but I
don't know yet.<br></div>
<div>I would like the receiver to get all of the performance it could, out of
that A->D converter.<br></div>
<div> </div>To be a competitive receiver-exciter, I am concerned
about<br></div>1.) The loss in input NF because of the oscilloscope input versus
a properly designed 50 Ohm input.<br></div>
<div>2.) Lack of appropriate Nyquist filters.<br></div>3.) The poor frequency
stability of the on-board sampling clock.<br></div>4.) The poor phase noise
performance of the on-board sampling clock.<br></div>5.) Moving the sampling
clock to the telecom frequency ladder, ie., 122.88 MHz<br><br></div>I don't know
that all of these are issues, just what I am worried about, and would need to
verify/test.<br></div>
<div>I am making assumptions as to how they implemented the oscilloscope inputs,
and could easily be wrong.<br><br></div>
<div>When I say poor, I don't mean that the Red Pitaya is not good for its
intended purpose, which I am<br></div>
<div>sure that it is, but poor relative to the performance I personally expect
out of an SDR.<br><br></div>
<div>It might be possible to hack in a different front end connection to deal
with (1 and 2).<br><br></div>It might be possible to hack in a better external
sampling reference clock, that would deal with (3, 4, and 5).<br><br></div>I am
sure that you would need at least 6 layer board, maybe 8 layers to interface to
the Zync BGA, so<br></div>a re-layout would not be trivial.<br><br></div>I am
very interested in what Terry finds out about the LF
spurs.<br><br></div>Thanks,<br></div>--- Graham<br><br>==<br>
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