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    <p>Hi All,</p>
    <p>What I understand from the Teamspeak discussions is that one of
      the big advantages also is that the development of software is
      "easier" for PC related software than  for FPGA software. (long
      compile times and critical timing issues etc. for FPGA)  and that
      a many more people know how to develop software for a PC than for
      FPGA's and so many more people could contibute.<br>
    </p>
    <p>@Helmut:  I thought 10 GBit was mentioned as a possibility?<br>
    </p>
    <p>73,<br>
    </p>
    Henry - PA0HJA<br>
    <br>
    <br>
    <br>
    <div class="moz-cite-prefix">On 12-5-2016 15:40, n3evl wrote:<br>
    </div>
    <blockquote
      cite="mid:3a0c7633-a2b9-fc25-7ede-0b11557271b1@townisp.com"
      type="cite">
      <pre wrap="">***** High Performance Software Defined Radio Discussion List *****

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      <p>Sounds interesting.  I recall some early discussions relating
        to DFC that I think initially had the objective of minimizing
        the involvement of the FPGA but this sounds even better!  I must
        admit I am way behind listening to my TeamSpeak recordings. 
        Looking forward to see what Phil has to say.</p>
      <p>Pete, N3EVL<br>
      </p>
      <div class="moz-cite-prefix">On 5/12/2016 9:27 AM, Scott Traurig
        wrote:<br>
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cite="mid:CAGK9zXqiXA47iqhhHahTj3vmi+=uihJ7fQUzMDsWo5ibn-sDvA@mail.gmail.com"
        type="cite">
        <div dir="ltr">I believe Phil's efforts on DFC are wholly
          focused on his new circuit card design that I think he intends
          to present at Friedrichshafen this June, based on Teamspeak
          discussions. This card will take raw ADC output and put it
          directly onto a PCIE bus for processing in an NVIDIA GPU (CUDA
          processing) also resident on the same PCIE bus. The great
          advantage of this, of course, is that such an architecture
          would eliminate the requirement for complex and expensive FPGA
          processing, and thereby also open up development of what used
          to be FPGA firmware to C developers.
          <div><br>
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          <div>73,</div>
          <div><br>
          </div>
          <div>Scott/w-u-2-o</div>
          <div><br>
          </div>
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        <div class="gmail_extra"><br>
          <div class="gmail_quote">On Thu, May 12, 2016 at 8:55 AM,
            n3evl <span dir="ltr"><<a moz-do-not-send="true"
                href="mailto:n3evl@townisp.com" target="_blank">n3evl@townisp.com</a>></span>
            wrote:<br>
            <blockquote class="gmail_quote" style="margin:0 0 0
              .8ex;border-left:1px #ccc solid;padding-left:1ex">*****
              High Performance Software Defined Radio Discussion List
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                <p>I'm also curious about DFC, specifically, what will
                  the minimum <i>radio </i>hardware requirements be? 
                  I currently have an Atlas based system but seem to
                  recall that, at least for the moment, this hardware
                  will not support the new protocol and I think the new
                  protocol is essential for DFC.  Should I be thinking
                  of investing in a Hermes (or Hemes derivative) based
                  radio in order to take advantage of DFC?</p>
                <p>Pete, N3EVL<br>
                </p>
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