[hpsdr] Plans...

[Philip Covington]

On 4/5/06, Larry Gadallah <lgadallah at gmail.com> wrote:

> I don't know if anyone has addressed this, but to me the heart of the system
> will be the ADC, and as time passes the performance of the ADC devices will
> get better and better. I apologize if this is a dumb question, but has
> anyone done some crystal-ball gazing to verify that everything ( i.e. buses,
> data widths, clock rates) will work with, for example, a future 250 MSPS
> 20-bit ADC rather than a 130 MSPS 16-bit? Having said that, the project
> seems to be well ensconced in the hands of a set of veritable hardware
> geniuses  :-). Thanks Phil, Eric, Lyle, et al.
>
> 73,
> --
> Larry Gadallah, VE6VQ/W7
> lgadallah AT gmail DOT com

Hi Larry,

My plan for the Mercury board is to have a Cyclone II FPGA on board to
do the Digital Down Conversion (DDC) functions.  The output of the
Mercury board (initially) would then be a serial data stream to mimic
the Janus board... maybe at up to 250 - 500 kSPS. The next step would
be a future Mercury II board with a Stratix II GX (if..when...the
prices come down) so we can have a PCI Express link to a PC instead of
USB 2.

The advantage of having the Mercury output a slower data stream like
the Janus is that we can use the DSP board in both cases for PC-less
applications.

I also might make the provision to optionally have a FX2 on the
Mercury board so it could be stand alone for applications where you
what higher data rates (up to what USB 2 can support).  I haven't
decided on that yet...

73 de Phil N8VB