[hpsdr] Janus Prototype Status

[Bill Tracey]

Just a quick note out here on progress on the Janus (I/Q. mic, and monitor 
IO) work going on as we've been a little quiet out here of late.

The Wolfon and PCM4202  chips have been built and tested with a Xylo and 
PowerSDR in a 2in, 2out configuration at 48 khz and seem to be working 
pretty well.  The PCM 4202 looks to be better than the Wolfson in terms of 
performance and is a bit easier to deal with.

Work is ongoing on the Cirrus CS 5381   VK Phil and I have both built 
CS5381 prototypes - mine seemed a bit spurry, so Phil's done one now as 
well and initially saw some of the same spur issues I did.  The CS5381 
seems to be very sensitive to the input stage in front of it, and Phil has 
now puit a front end in front of his CS5381.  Still has some issues,  but 
the noise floor looks spectacular (close to -160 dbm on Phil's 
latest).   Next step on the 5381 is for Phil to build the opamp input stage 
Cirrus recommends in their app notes.  It calls for some specific op amps 
from LT that I've  ordered and will FedEx them to Phil as soon as they come 
in -- will probably be next week by the time he gets 'em.     By the time 
Phil gets done the CS5381 may be the best performer - but the additional 
complexity and cost (2x for the A/\D compared to the PCM4202, plus 4 op 
amps at $5 each) may make us decide to use the PCM4202.  As Phil puts it we 
may get 10 db better performance but at a 30 db increase in cost and 
aggravation.

We will do the bake off on the chips at 48 and 96 klhz  - and perhaps 192 
khz.  Don't want to find out we've got a Presonus style 24 khz roll off 
problem on one of these after the fact.  We've got FPGA code for 48 and 96, 
PowerSDR code for 48khz 2in 2out - I'm currently working on 3in 4out at 
48khz for PowerSDR and will then move on to 96 khz so we can do the bake 
off.

Regards,

Bill  



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