[hpsdr] FPGA power management

[Philip Covington]

On 4/13/06, Horst Gruchow <horst at needles.de> wrote:
> Hi, Phil and the group
>
> recently I found an interesting article about power management of Altera FPGAs:
>
> http://dkc3.digikey.com/PDF/Marketing/FPGA_Altera.pdf
>
> I don't know whether anybody was aware of this or not. Therefore I thought of posting it here.
>
> They say that Altera is generally recommending power sequencing of first switching on core voltage followed by I/O power.
>
> As I personally do not yet have any practical experience in this matter what are your thoughts and experiences with this?
> Is it really needed.? Obviously you did not implemented this feature in the FPGA_USB design.
> I did not see this feature in other designs either except for the original Altera evaluation boards.
>
> Maybe we should consider something similar in order to have a well defined powering up of the FPGA_USB board.
>
> Just my few EURO cents of thoughts.
>

If I were dealing with some of the larger Altera parts such as the
Stratix II I would look at power sequencing more seriously.  For our
Cyclone II we don't need it.  Actually we already have power
sequencing built in by feeding the FAN1112 from the 3.3V regulator. 
VCCINT will be up before the VCCIO.

73 de Phil N8VB

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