[hpsdr] FPGA power management

[H. Gruchow]

Philip Covington wrote:

> 
> If I were dealing with some of the larger Altera parts such as the
> Stratix II I would look at power sequencing more seriously.  For our
> Cyclone II we don't need it.  

Hi, Phil and the group

thanks for your comment on power management. That's what I thought that we really don't 
need this somewhat complex power management. I reviewed the schematic of the Altera 
Cyclone II DSP evaluation board. The schematic for power management takes up one whole 
page by itself. The FPGA is an EP2C35F672.

 > Actually we already have power
 > sequencing built in by feeding the FAN1112 from the 3.3V regulator.
 > VCCINT will be up before the VCCIO.

As far as I understand your circuit the LD1117 is delivering the VCCIO and the FAN1112 
does the 1.2Volt VCCINT (or core voltage). This means that VCCIO will be up before the 
core voltage (just opposite to what Altera recommends).
Don't misunderstand me. I don't want to bug you with this or keep you away from designing 
the pcb for the fpga_usb (go, go, go, do it) :-) . It is just for my personal understanding.

My not so honest recommendation for a delay line:
You will have to build in a 1 foot long runway for the electrons between power-in and the 
input of the LD1117 in order to reach the LD1117 after FAN1112. This could be done easily 
with our board dimensions of 100x100mm guiding the 5Volt power all around the board over 
three sides which gives 100+100+100 mm or 1 foot (just joking).

By the way, you have done a great job on the ATLAS board and of course a fantastic job on 
the fpga_usb design. My compliments on this and

Happy Easter to everyone

73
Horst
DL6KBF

 1145029822.0