[hpsdr] Question on Janus/OZY function integration

[pvharman at arach.net.au]

Hi Ray,

The FPGA on the Janus board is in fact a CPLD (i.e. a small FPGA). It's real 
purpose is to give us total flexibility in the future as to what pins we use 
on the Altas bus to get data into and out of Janus. Since we have lots of 
spare room in it I have used some to generate clocks and also phase lock the 
clock to a 10MHz source. We could just as easily done all this in hte Ozy FPGA.

Your second drawing is how we developed the prototype using a Xylo FPGA board 
so - yes - it will work. 





Quoting Ray Anderson <ray.anderson at xilinx.com>:

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