[hpsdr] Question on Janus/OZY function integration

[Christopher T. Day]

Ray,

 

I'll try to answer and then the experts can jump all over me.

 

Your Janus/Ozy architecture is almost right, but the PWD lines are in
the wrong direction; they actually are from the Cyclone II FPGA on the
Ozy board to the Janus board. What they are for, as I understand it, is
to take the processed I/Q data being returned from the PC and convert it
to analog for the output earphone amplifier of the TLV320AIC23B CODEC on
the Janus board. The Max II CPLD on the Janus board is doing nothing
much at the moment besides cross-connecting Atlas bus signals to
internal Janus signals. It's the Cyclone II FPGA on the Ozy board that
receives the 24-bit I/Q digital data and turns it into PWM data on the
Atlas bus; I don't think it's filtered here, so it is analog in timing
but digital in amplitude. That signal is then routed through the Max II
CPLD on Janus to be filtered to AM and fed to the amplifier on the Janus
board. So in your drawing, the PWM arrow points the other way and the
signals go through the EPM240.

 

Anyway, given that you can squeeze in all on a board, the Phoenix
architecture is fine, again with the PWM arrow reversed and connected to
the FPGA. These are not physically small chips, and there are a _lot_ of
traces.

 

Let the stone throwing begin.

 

 

            Chris - AE6VK

 

 

  _____  

From: Ray Anderson [mailto:ray.anderson at xilinx.com] 
Sent: Wednesday, August 02, 2006 12:02 PM
To: hpsdr at hpsdr.org
Subject: [hpsdr] Question on Janus/OZY function integration

 

 

I'd like to pose a question to the FPGA/Verilog gurus on the list.

 

The simplified block diagram found at the following URL illustrates the
current Janus/OZY architecture as I understand it with regards to the
connectivity between the analog inputs and outputs and the USB I/O:
http://wb6tpu.googlepages.com/janusozysimplifiedblockdiagram

 

 

Noting that there is an FPGA on both the Janus and the OZY boards, I am
wondering if it is practical to do away with one of them if the
equivalent analog to USB connections were to be integrated on the
Phoenix board. Please see the simplified block diagram at the following
URL that illustrates what I am thinking of:
http://wb6tpu.googlepages.com/proposedphoenixintegrateblockdiagram

 

 

73s  de Ray       WB6TPU

 

 

 

 

 

 

 

 

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