[hpsdr] Question on Janus/OZY function integration

[Ray Anderson]

I'd like to pose a question to the FPGA/Verilog gurus on the list.

 

The simplified block diagram found at the following URL illustrates the
current Janus/OZY architecture as I understand it with regards to the
connectivity between the analog inputs and outputs and the USB I/O:
http://wb6tpu.googlepages.com/janusozysimplifiedblockdiagram

 

 

Noting that there is an FPGA on both the Janus and the OZY boards, I am
wondering if it is practical to do away with one of them if the
equivalent analog to USB connections were to be integrated on the
Phoenix board. Please see the simplified block diagram at the following
URL that illustrates what I am thinking of:
http://wb6tpu.googlepages.com/proposedphoenixintegrateblockdiagram

 

 

73s  de Ray       WB6TPU

 

 

 

 

 

 

 

 

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