[hpsdr] OZy Speed Test

[Philip Covington]

On 8/4/06, Eric Blossom <eb at comsec.com> wrote:
> On Fri, Aug 04, 2006 at 04:21:23PM -0400, Philip Covington wrote:
> > ***** High Performance Software Defined Radio Discussion List *****
> >
> > On 8/4/06, Philip Covington <p.covington at gmail.com> wrote:
> > > If anyone wants to try the transfer speed test you need to load
> > > fifo_test.rbf and run fifo_test.exe (both can be found in SVN).  The
> > > OZYV1FW08042006-1.hex file should not be used with JANUS yet because I
> > > set the FX2 clock speed back up to 48 MHz from 24 MHz.  If you do load
> > > this firmware revision you'll notice that the FPGA upload times are
> > > halved (as expected).
> > >
> > > 73 de Phil N8VB
> >
> > Update:
> >
> > With the new utility files and firmware in SVN (and on my website) you
> > can now change the CPU speed on the fly via a vendor request.
> > setCPU_12MHZ.bat, setCPU_24MHZ.bat, and setCPU_48MHZ.bat shows how to
> > use the set_CPUSpeed.exe utility.
> >
> > You can now use OZYV1FW08042006-1.hex, but just remember to set the
> > CPU speed to the value you think you need.
> >
> > 73 de Phil N8VB
>
> Any particular reason you're not running it at 48 MHz all the time?
> I know it burns more power, but is it that significant?
>
> Eric K7GNU
>

Eric,

It is primarily for testing.

The reason I allowed for the option to run the CPU other than 48 MHz
is that the Xylo board, which was used in the development of the JANUS
card, was run at 24 MHz.  Phil H or Bill T will probably be able to
tell you why they used 24 MHz - I am not sure.  As I recall there was
some issue with running it at 48 MHz.   The Xylo tied the CLKOUT and
the IFCLK pins together to feed CLK0 on the Cyclone.  In the Xylo's
FX2 firmware I assume there was the ability to switch which source was
clocking the FPGA.  I could never get a straight answer out from the
Xylo designer as to whether he was using async or sync slave FIFO
mode.  If the CLKOUT was driving the FPGA and async mode was used,
then I could see how the CPU clock speed would affect the transfer
over the high speed endpoints (because of the timing requirements of
the SLRD and SLWR lines in async mode which is almost met at 24 MHz).

To ease the transfer of code from Xylo-Janus to OZY-Janus, Phil and
Bill wanted to keep everything in the OZY (as far as endpoints and
speed) as close as possible to what they had with Xylo.  Once the
OZY-Janus combo is up and running then we can improve things.

73 de Phil N8VB

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