[hpsdr] Cyclone II with Nios core for SDR

[Murray Lang]

I'm currently trying to get my head around FPGA matters using the Altera 
Cyclone II development board pointed out to this list by Phil VK6APH. The 
project I have in mind is to use it as an SDR back end, employing a NIOS 
DSP IP core within the FPGA for *all* of the number crunching. I note that 
Cyclone IIs are used within the HPSDR project but seemingly not for their 
DSP capability. Can anyone with experience in these matters tell me whether 
I'd be wasting my time trying to, say, port DttSP to the Nios core to get a 
complete, useable SDR back end without additional processing power?

Thanks in advance,

Murray - VK6HL


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