[hpsdr] Cyclone II with Nios core for SDR

[Sattler, Jay]

Hi Murray-
I can tell you you would not be wasting your time just based on the new
knowledge you would have gained in the endeavor!  However, I'm not
familiar with DttSP, so I'm not sure what it would take to get it
operational.  My experience is mainly with the Xilinx cores and I've
even written a couple of FPGA based OS's myself.  They bottle neck is
usually memory constraints.  A lot of the larger FPGA's now have memory
blocks and that will help some but it will just depend on the overall
size requirements of DttSP.  Also, you will need to investigate the code
to see is there is any type of interprocess communication etc, I'm not
sure NiOS has that type of functionality.  I'm sure some other folks
that know the pieces better will be able to shed more insight on your
project.      

-----Original Message-----
From: hpsdr-bounces at hpsdr.org [mailto:hpsdr-bounces at hpsdr.org] On Behalf
Of Murray Lang
Sent: Sunday, December 10, 2006 8:33 PM
To: hpsdr at hpsdr.org
Subject: [hpsdr] Cyclone II with Nios core for SDR


***** High Performance Software Defined Radio Discussion List *****

I'm currently trying to get my head around FPGA matters using the Altera

Cyclone II development board pointed out to this list by Phil VK6APH.
The 
project I have in mind is to use it as an SDR back end, employing a NIOS

DSP IP core within the FPGA for *all* of the number crunching. I note
that 
Cyclone IIs are used within the HPSDR project but seemingly not for
their 
DSP capability. Can anyone with experience in these matters tell me
whether 
I'd be wasting my time trying to, say, port DttSP to the Nios core to
get a 
complete, useable SDR back end without additional processing power?

Thanks in advance,

Murray - VK6HL

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