[hpsdr] Cyclone II with Nios core for SDR - Correction

[Murray Lang]

Just so that people aren't duped into buying something based on 
misleading information I've provided:
It turns out that the Nios Embedded Design Suite supplied with...
    
http://www.altera.com/products/devkits/altera/kit-cyc2-2C20N.html#documentation
...*doesn't* include the uC/OS RTOS, despite what's claimed in...
    
http://www.altera.com/products/ip/processors/nios2/tools/ni2-development_tools.html

Maybe the download version has it (I'll know tomorrow), but at any rate 
what the local distributer tells me that the resulting binaries cannot 
be distributed for *any* purpose, commercial or otherwise, without 
purchasing the very expensive licence. The Altera site only says that 
they can't be distributed for commercial purposes.

Bugger. Still a very useful kit, but the RTOS would have made life a lot 
easier for SDR purposes.

Murray

Murray Lang wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Hi Jay,
> I know that you learn most from failures, but I need to be selective 
> with my spare time these days.
> I've only just discovered DttSP myself, but it seems as good a place as 
> any to start. Nios is a DSP IP (Intellectual Property not Internet 
> Protocol) core that drops into a Cyclone II FPGA and takes advantage of 
> that FPGAs specialised multiplier elements. The development kit also 
> comes with a Nios port of the uC/OS-II RTOS, which seems to have all of 
> the threading and synchronisation primitives you would need. There's 
> plenty of memory on the development board.
>  
> I suspect it would be more painstaking than difficult - replace POSIX 
> thread and synch calls with uC/OS equivalents; replace FTTW calls with 
> whatever the Nios libraries provide; replace I/O calls (now that could 
> be painful). The biggest problems I've had in the past with porting 
> between operating systems (apart from GUI inconsistencies) is where a 
> different thread scheduling algorithm exposes incorrectness in thread 
> synchronisation that didn't manifest in the original. Since DttSP has 
> already been ported between Linux and Win32, any such bugs should have 
> been smoked out.
>
> Anyway, in the absence of alarm bells I'll push ahead.
>
> Murray
>
> Sattler, Jay wrote:
>   
>> Hi Murray-
>> I can tell you you would not be wasting your time just based on the new
>> knowledge you would have gained in the endeavor!  However, I'm not
>> familiar with DttSP, so I'm not sure what it would take to get it
>> operational.  My experience is mainly with the Xilinx cores and I've
>> even written a couple of FPGA based OS's myself.  They bottle neck is
>> usually memory constraints.  A lot of the larger FPGA's now have memory
>> blocks and that will help some but it will just depend on the overall
>> size requirements of DttSP.  Also, you will need to investigate the code
>> to see is there is any type of interprocess communication etc, I'm not
>> sure NiOS has that type of functionality.  I'm sure some other folks
>> that know the pieces better will be able to shed more insight on your
>> project.      
>>
>> -----Original Message-----
>> From: hpsdr-bounces at hpsdr.org [mailto:hpsdr-bounces at hpsdr.org] On Behalf
>> Of Murray Lang
>> Sent: Sunday, December 10, 2006 8:33 PM
>> To: hpsdr at hpsdr.org
>> Subject: [hpsdr] Cyclone II with Nios core for SDR
>>
>>
>> ***** High Performance Software Defined Radio Discussion List *****
>>
>> I'm currently trying to get my head around FPGA matters using the Altera
>>
>> Cyclone II development board pointed out to this list by Phil VK6APH.
>> The 
>> project I have in mind is to use it as an SDR back end, employing a NIOS
>>
>> DSP IP core within the FPGA for *all* of the number crunching. I note
>> that 
>> Cyclone IIs are used within the HPSDR project but seemingly not for
>> their 
>> DSP capability. Can anyone with experience in these matters tell me
>> whether 
>> I'd be wasting my time trying to, say, port DttSP to the Nios core to
>> get a 
>> complete, useable SDR back end without additional processing power?
>>
>> Thanks in advance,
>>
>> Murray - VK6HL
>>
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>>     
>
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