[hpsdr] HPSDR Block Diagram

[pvharman at arach.net.au]

Hi Alex,

There are a number of things that I don't understand in relation to your 
CASMIR design.

1. The I/Q inputs to the mixers appear to come from the Atlas bus. Are you 
proposing the use the I and Q PWM signals and low pass filter them on your 
board. Is this what the AD8132s are for? In which case what are the amplifiers 
between the FPGA and PI5V331 for?

2. The AD8345 seems to cover 140MHz at the low end - will it work at 50MHz?

3. I assume the PI5V331 is being used at a QSE - at 10nS switching time are 
they fast enough? 

4. Will the outputs of the AD9512 drive the AD8349 without additional 
interface chips?

5. The current LO ideas are for either a DDS or dividing down a 2.4GHz 
oscillator. Since the LO inputs to the AD9512 are all ready in I/Q format how 
does this divider scheme work? 

6. What output power levels are you expecting from the board?  Should a MIMC 
be added to each output so that the filters are buffered from any load 
variations?

7. Why use bandpass filters for the HF outputs, won't the sprogs from the QSE 
be harmonics so LPFs could be used?

8. Will the PI3B3251 switches handle the signal levels we expect?

9. May need to allow different LO inputs for HF and above.

10. Why not run 50MHz out of the QSE?

More questions to follow. I think that a white paper explaining your concepts 
would really help the review process. 

73's Phil...VK6APH 



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