[hpsdr] HPSDR Block Diagram

[Alex]

Phil,

Thanks! My comments are in-line.

----- Original Message ----
From: pvharman at arach.net.au
To: Alex <harvilchuck at yahoo.com>
Cc: Philip Covington <p.covington at gmail.com>; hpsdr at hpsdr.org
Sent: Thursday, July 6, 2006 11:38:46 PM
Subject: Re: [hpsdr] HPSDR Block Diagram

Hi Alex,

There are a number of things that I don't understand in relation to your 
CASMIR design.

1. The I/Q inputs to the mixers appear to come from the Atlas bus. Are you 
proposing the use the I and Q PWM signals and low pass filter them on your 
board. Is this what the AD8132s are for? In which case what are the amplifiers 
between the FPGA and PI5V331 for?


This portion of the circuit is directly lifted from JANUS. CASMIR is going to handle the I/Q PWM exactly the same was JANUS is (plus I was going to reuse your VHDL). The amplifiers just after the FPGA are the NE5532D's from JANUS. I left them in for now. 


2. The AD8345 seems to cover 140MHz at the low end - will it work at 50MHz?


Regretably not. 140MHz is at the bottom end of it's capabilities.


3. I assume the PI5V331 is being used at a QSE - at 10nS switching time are 
they fast enough? 


The second PI5V331 is being used as the QSE. It only has to do up to 75MHz to support the 4m band. 
It can either be the FST3253 or the PI5V331, both are used in numerous designs from Gerald's QEX articles to WB6DHW's circuit (and many other designs on the internet)


4. Will the outputs of the AD9512 drive the AD8349 without additional 
interface chips?


I did not finish the LO distribution portion of the design since it's still up in the air where the LO is coming from. The AD9512 has 5 outputs.


5. The current LO ideas are for either a DDS or dividing down a 2.4GHz 
oscillator. Since the LO inputs to the AD9512 are all ready in I/Q format how 
does this divider scheme work? 


We need a decision on the LO generation. Some comments say it's going to be centrally generated, some comments say each board needs to generate their own LO. 
This is why I halted work on the LO distribution and just put the design out for comments. 


6. What output power levels are you expecting from the board?  Should a MIMC 
be added to each output so that the filters are buffered from any load 
variations?

Yes, a MIMC needs to be added for each of the outputs. Higher power levels need to be generated in an external circuit. I'll add it to the CASMIR issues list.


7. Why use bandpass filters for the HF outputs, won't the sprogs from the QSE 
be harmonics so LPFs could be used?


I'm going with the "standard design" here. All examples I have investigated on the internet have been using BPFs (CDG2000, T03DSP, SDR-1000, etc.). It might be worth doing a little experimentation.


8. Will the PI3B3251 switches handle the signal levels we expect?


They should, but I've got a call in with Pericom to discuss


9. May need to allow different LO inputs for HF and above.


I have an issue I created against the design that I need to add a LO port for tower mounted microwave amplifiers and upconverters 


10. Why not run 50MHz out of the QSE?

50MHz and 70MHz are coming out of the QSE already. I'm rerouting the outputs to the VHF and up output connector

More questions to follow. I think that a white paper explaining your concepts 
would really help the review process. 


I updated the Wiki yesterday with a narrative of the design.




73's Phil...VK6APH 






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