[hpsdr] bypass caps

[Jeroen Bastemeijer]

Dear All,

I'm reading a lot off discussions about the self-inductance caused by 
PCB tracks and so on leading to capacitors. Using a large surface area 
will lower the self-inducttance, true. However, instead of using a large 
area (either bij large diameter (via's) or by using wide tracks) there 
is another solution. Parallelling multiple "inductors", so instead of 
using one big hole, a large numer of small holes (probably consuming the 
same amount of baord-space) will give the same or a better result. The 
same is true for parallelling multiple PCB tracks. This will give less 
coupling capacitance to e.g. other tracks......

I did some research into ground-leads (part of an ESD protection 
project) and it turned out that it was better to use a multicore (each 
core insulated) cable than a "solid" copper cable with the same 
diameter. The parallel inductance of the single thin wires together 
turned out to give better performance than a very thick, not so 
flexible, copper cable.
Hope this might add something usefull for the discussion/design. Good luck!

Best regards, 73's, Jeroen PE1RGE

Ray Anderson wrote:

>***** High Performance Software Defined Radio Discussion List *****
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>>.Thanks a million for the links to the papers Ray, they have been very
>>informative.
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>>One thing that I haven't come across is the size of the via (drill
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>size).  >I would think for the lowest impedance, you would want as large
>a drill >size you can have for the layout.  The same could be said for
>inductance, >the larger the drill, the lower the inductance.  Any
>thoughts on via sizes?
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>>In the Xilinx app note, how did they calculate the percentages in Table
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>6?  
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>>- Steve N7HPR
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>Steve-
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>The mounted inductance of a decoupling capacitor is comprised of several
>partial inductances: the intrinsic inductance of the capacitor itself
>(what the capacitor marketeers put in their databook), the vertical
>inductance contributed by the vias, and the horizontal inductance
>(spreading inductance of the planes).
>
>In the grand scheme of things the intrinsic inductance is pretty small,
>the vertical inductance is a smallish number too (unless you have a very
>thick stackup where it then becomes significant), the spreading
>inductance is a function of both the separation between the planes and
>the mounting pads escape geometry.
>
>So, yes you can minimize via inductance if you have a large hole in the
>via (since the majority of the current will flow on the outer surface of
>the 'pipe') however unless the stackup is pretty thick and stacked such
>that you need to descend deeply into the stack then the via contribution
>will be a relatively small part of the total inductance.
>
>Another thing to consider is that if you have a large diameter via drill
>you will also need larger diameter via pads and anti-pads. The larger
>anti-pads will effectively 'swiss cheese' the associated planes if there
>are a significant number of them and can increase the spreading
>inductance by as much as a factor of 3-4 X  (there ain't no free
>lunch!). Large diameter vias also can't be put real close together so
>you are limited in the ability to minimize the current loop size.
>
>>From a practical standpoint, to minimize decap inductance I've found it
>best to:
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>	1) Keep the vias short (i.e. place planes near the surface of 
>         The stackup)
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>	2) Keep your mounting pad escapes close together and short
>(broadside
>         escapes work well)
>
>	3) Use multiple escapes and vias per pad.
>
>Regarding Table 6 in the Xilinx app note:
>
>	I think someone came up with those numbers empirically. I
>wouldn't put much stock in them. There are several ways to determine how
>many decaps you need. Rule-of-thumb tables aren't one of the preferred
>methods.
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>See the following Designcon papers by Steve Weir and Scott McMorrow
>(terraspeed Consulting) for a good treatment of decoupling capacitor
>selection:
>http://www.teraspeed.com/papers/High%20Performance%20FPGA%20Bypass%20Fil
>ter%20Networks%20Paper.pdf
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>http://www.teraspeed.com/papers/capacitor_placement_public.pdf
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>They discuss via inductance calculations amongst other factors.
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>Also see the papers Istvan Novak (Sun Microsystems) has on his web site:
>
>http://home.att.net/~istvan.novak/papers.html
>
>
>-Ray	WB6TPU
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-- 
Ing. Jeroen Bastemeijer

Delft University of Technology
Department of Electrical Engineering
Electronic Instrumentation Laboratory
Mekelweg 4, Room 13.090
2628 CD Delft
The Netherlands

Phone: +31.15.27.86542
Fax: +31.15.27.85755
E-mail: J.Bastemeijer at EWI.TUDelft.nl

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