[hpsdr] Janus ESD terminations

[FRANCIS CARCIA]

I plan to get a supply of small chip resistors and lay them in across the connector pins A row to B row  then C row to B row.  The layout is tight and the connector field looks like the best spot. It is a real drag to blow out an FPGA with ESD. No smoke just a trace of package heat......I don't have a good repair person in the shack like at work. gfz
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