[hpsdr] Xilinx Coregen DDS
Leon Heller
leon.heller at bulldoghome.com
Wed Jun 14 03:56:30 PDT 2006
As an exercise, I tried generating the simplest possible DDS with the
CoreGen - 100 MHz clock input, fixed 5 MHz single sine output, six bits.
Here is the VHDL it generated:
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be
--
-- solely for design, simulation, implementation and creation
--
-- design files limited to Xilinx devices or technologies.
--
-- with non-Xilinx devices or technologies is expressly
ted --
-- and immediately terminates your
--
--
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS
--
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS
--
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR
TION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
--
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT
--
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
--
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
E --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS
--
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF
--
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES
--
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS
--
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
--
-- FOR A PARTICULAR
--
--
--
-- Xilinx products are not intended for use in life
--
-- appliances, devices, or systems. Use in such applications
--
-- expressly
--
--
--
-- (c) Copyright 1995-2005 Xilinx,
--
-- All rights
--
--------------------------------------------------------------------------------
-- synopsys translate_off
LIBRARY std, ieee;
USE std.standard.ALL;
USE ieee.std_logic_1164.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY XilinxCoreLib;
USE XilinxCoreLib.c_reg_fd_v7_0_comp.ALL;
USE XilinxCoreLib.blkmemsp_v6_0_comp.ALL;
USE XilinxCoreLib.c_shift_fd_v7_0_comp.ALL;
USE XilinxCoreLib.c_addsub_v7_0_comp.ALL;
ENTITY dds IS
PORT (
CLK : IN STD_LOGIC;
SINE : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END dds;
ARCHITECTURE xilinx OF dds IS
-- Signals for connecting to instantiations
SIGNAL BU4_A : STD_LOGIC_VECTOR(27 DOWNTO 0);
SIGNAL BU4_Q : STD_LOGIC_VECTOR(27 DOWNTO 0);
SIGNAL BU4_CLK : STD_LOGIC;
SIGNAL BU183_D : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU183_Q : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU183_CLK : STD_LOGIC;
SIGNAL BU175_addr : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU175_clk : STD_LOGIC;
SIGNAL BU175_din : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU175_dout : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU175_en : STD_LOGIC;
SIGNAL BU175_nd : STD_LOGIC;
SIGNAL BU175_rfd : STD_LOGIC;
SIGNAL BU175_rdy : STD_LOGIC;
SIGNAL BU175_sinit : STD_LOGIC;
SIGNAL BU175_we : STD_LOGIC;
SIGNAL BU198_D : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU198_Q : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL BU198_CLK : STD_LOGIC;
SIGNAL BU198_CE : STD_LOGIC;
SIGNAL BU212_CLK : STD_LOGIC;
SIGNAL BU212_SDOUT : STD_LOGIC;
SIGNAL n0 : STD_LOGIC := '0';
SIGNAL n1 : STD_LOGIC := '1';
SIGNAL n2 : STD_LOGIC;
SIGNAL n3 : STD_LOGIC;
SIGNAL n4 : STD_LOGIC;
SIGNAL n5 : STD_LOGIC;
SIGNAL n6 : STD_LOGIC;
SIGNAL n7 : STD_LOGIC;
SIGNAL n8 : STD_LOGIC;
SIGNAL n9 : STD_LOGIC;
SIGNAL n10 : STD_LOGIC;
SIGNAL n11 : STD_LOGIC;
SIGNAL n12 : STD_LOGIC;
SIGNAL n13 : STD_LOGIC;
SIGNAL n14 : STD_LOGIC;
SIGNAL n15 : STD_LOGIC;
SIGNAL n16 : STD_LOGIC;
SIGNAL n17 : STD_LOGIC;
SIGNAL n18 : STD_LOGIC;
SIGNAL n19 : STD_LOGIC;
SIGNAL n20 : STD_LOGIC;
SIGNAL n21 : STD_LOGIC;
SIGNAL n22 : STD_LOGIC;
SIGNAL n23 : STD_LOGIC;
SIGNAL n24 : STD_LOGIC;
SIGNAL n25 : STD_LOGIC;
SIGNAL n26 : STD_LOGIC;
SIGNAL n27 : STD_LOGIC;
SIGNAL n28 : STD_LOGIC;
SIGNAL n29 : STD_LOGIC;
SIGNAL n36 : STD_LOGIC;
SIGNAL n37 : STD_LOGIC;
SIGNAL n38 : STD_LOGIC;
SIGNAL n39 : STD_LOGIC;
SIGNAL n40 : STD_LOGIC;
SIGNAL n41 : STD_LOGIC;
SIGNAL n42 : STD_LOGIC;
SIGNAL n381 : STD_LOGIC;
SIGNAL n382 : STD_LOGIC;
SIGNAL n383 : STD_LOGIC;
SIGNAL n384 : STD_LOGIC;
SIGNAL n385 : STD_LOGIC;
SIGNAL n386 : STD_LOGIC;
SIGNAL n387 : STD_LOGIC;
SIGNAL n388 : STD_LOGIC;
SIGNAL n389 : STD_LOGIC;
SIGNAL n390 : STD_LOGIC;
SIGNAL n391 : STD_LOGIC;
SIGNAL n392 : STD_LOGIC;
SIGNAL n393 : STD_LOGIC;
BEGIN
n36 <= CLK;
SINE(0) <= n37;
SINE(1) <= n38;
SINE(2) <= n39;
SINE(3) <= n40;
SINE(4) <= n41;
SINE(5) <= n42;
BU4_A(0) <= n2;
BU4_A(1) <= n3;
BU4_A(2) <= n4;
BU4_A(3) <= n5;
BU4_A(4) <= n6;
BU4_A(5) <= n7;
BU4_A(6) <= n8;
BU4_A(7) <= n9;
BU4_A(8) <= n10;
BU4_A(9) <= n11;
BU4_A(10) <= n12;
BU4_A(11) <= n13;
BU4_A(12) <= n14;
BU4_A(13) <= n15;
BU4_A(14) <= n16;
BU4_A(15) <= n17;
BU4_A(16) <= n18;
BU4_A(17) <= n19;
BU4_A(18) <= n20;
BU4_A(19) <= n21;
BU4_A(20) <= n22;
BU4_A(21) <= n23;
BU4_A(22) <= n24;
BU4_A(23) <= n25;
BU4_A(24) <= n26;
BU4_A(25) <= n27;
BU4_A(26) <= n28;
BU4_A(27) <= n29;
n2 <= BU4_Q(0);
n3 <= BU4_Q(1);
n4 <= BU4_Q(2);
n5 <= BU4_Q(3);
n6 <= BU4_Q(4);
n7 <= BU4_Q(5);
n8 <= BU4_Q(6);
n9 <= BU4_Q(7);
n10 <= BU4_Q(8);
n11 <= BU4_Q(9);
n12 <= BU4_Q(10);
n13 <= BU4_Q(11);
n14 <= BU4_Q(12);
n15 <= BU4_Q(13);
n16 <= BU4_Q(14);
n17 <= BU4_Q(15);
n18 <= BU4_Q(16);
n19 <= BU4_Q(17);
n20 <= BU4_Q(18);
n21 <= BU4_Q(19);
n22 <= BU4_Q(20);
n23 <= BU4_Q(21);
n24 <= BU4_Q(22);
n25 <= BU4_Q(23);
n26 <= BU4_Q(24);
n27 <= BU4_Q(25);
n28 <= BU4_Q(26);
n29 <= BU4_Q(27);
BU4_CLK <= n36;
BU4 : C_ADDSUB_V7_0
GENERIC MAP (
c_has_bypass_with_cin => 0,
c_a_type => 1,
c_has_sclr => 0,
c_has_aset => 0,
c_has_b_out => 0,
c_sync_priority => 0,
c_has_s => 1,
c_has_q => 1,
c_bypass_enable => 1,
c_b_constant => 1,
c_has_ovfl => 0,
c_high_bit => 27,
c_latency => 1,
c_sinit_val => "0000000000000000000000000000",
c_has_bypass => 0,
c_pipe_stages => 0,
c_has_sset => 0,
c_has_ainit => 0,
c_has_a_signed => 0,
c_has_q_c_out => 0,
c_b_type => 1,
c_has_add => 0,
c_has_sinit => 0,
c_has_b_in => 0,
c_has_b_signed => 0,
c_bypass_low => 0,
c_enable_rlocs => 0,
c_b_value => "0000000000000000000000000000",
c_add_mode => 0,
c_has_aclr => 0,
c_out_width => 28,
c_low_bit => 0,
c_ainit_val => "0000000000000000000000000000",
c_has_q_ovfl => 0,
c_has_q_b_out => 0,
c_has_c_out => 0,
c_b_width => 28,
c_a_width => 28,
c_sync_enable => 0,
c_has_ce => 0,
c_has_c_in => 0
)
PORT MAP (
A => BU4_A,
Q => BU4_Q,
CLK => BU4_CLK
);
BU183_D(0) <= n24;
BU183_D(1) <= n25;
BU183_D(2) <= n26;
BU183_D(3) <= n27;
BU183_D(4) <= n28;
BU183_D(5) <= n29;
n381 <= BU183_Q(0);
n382 <= BU183_Q(1);
n383 <= BU183_Q(2);
n384 <= BU183_Q(3);
n385 <= BU183_Q(4);
n386 <= BU183_Q(5);
BU183_CLK <= n36;
BU183 : C_REG_FD_V7_0
GENERIC MAP (
c_width => 6,
c_has_ce => 0,
c_sinit_val => "000000",
c_has_sinit => 0,
c_ainit_val => "000000",
c_has_aset => 0,
c_sync_enable => 0,
c_enable_rlocs => 0,
c_has_aclr => 0,
c_has_sset => 0,
c_sync_priority => 0,
c_has_ainit => 0,
c_has_sclr => 0
)
PORT MAP (
D => BU183_D,
Q => BU183_Q,
CLK => BU183_CLK
);
BU175_addr(5) <= n386;
BU175_addr(4) <= n385;
BU175_addr(3) <= n384;
BU175_addr(2) <= n383;
BU175_addr(1) <= n382;
BU175_addr(0) <= n381;
BU175_clk <= n36;
BU175_din(5) <= '0';
BU175_din(4) <= '0';
BU175_din(3) <= '0';
BU175_din(2) <= '0';
BU175_din(1) <= '0';
BU175_din(0) <= '0';
n392 <= BU175_dout(5);
n391 <= BU175_dout(4);
n390 <= BU175_dout(3);
n389 <= BU175_dout(2);
n388 <= BU175_dout(1);
n387 <= BU175_dout(0);
BU175_en <= '0';
BU175_nd <= '0';
BU175_sinit <= '0';
BU175_we <= '0';
BU175 : blkmemsp_v6_0
GENERIC MAP (
c_sinit_value => "0000000000000000000",
c_yclk_is_rising => 1,
c_reg_inputs => 0,
c_has_en => 0,
c_ywe_is_high => 1,
c_ysinit_is_high => 1,
c_ytop_addr => "1024",
c_yprimitive_type => "4kx4",
c_yhierarchy => "hierarchy1",
c_has_rdy => 0,
c_has_limit_data_pitch => 0,
c_write_mode => 0,
c_width => 6,
c_yuse_single_primitive => 0,
c_has_nd => 0,
c_enable_rlocs => 0,
c_has_we => 0,
c_has_rfd => 0,
c_has_din => 0,
c_ybottom_addr => "0",
c_yen_is_high => 1,
c_pipe_stages => 0,
c_depth => 64,
c_has_default_data => 0,
c_limit_data_pitch => 18,
c_has_sinit => 0,
c_yydisable_warnings => 1,
c_mem_init_file => "dds_SINCOS_TABLE_TRIG_ROM.mif",
c_default_data => "0000000000000000000",
c_ymake_bmm => 0,
c_addr_width => 6
)
PORT MAP (
addr => BU175_addr,
clk => BU175_clk,
din => BU175_din,
dout => BU175_dout,
en => BU175_en,
nd => BU175_nd,
rfd => BU175_rfd,
rdy => BU175_rdy,
sinit => BU175_sinit,
we => BU175_we
);
BU198_D(0) <= n387;
BU198_D(1) <= n388;
BU198_D(2) <= n389;
BU198_D(3) <= n390;
BU198_D(4) <= n391;
BU198_D(5) <= n392;
n37 <= BU198_Q(0);
n38 <= BU198_Q(1);
n39 <= BU198_Q(2);
n40 <= BU198_Q(3);
n41 <= BU198_Q(4);
n42 <= BU198_Q(5);
BU198_CLK <= n36;
BU198_CE <= n393;
BU198 : C_REG_FD_V7_0
GENERIC MAP (
c_width => 6,
c_has_ce => 1,
c_sinit_val => "000000",
c_has_sinit => 0,
c_ainit_val => "000000",
c_has_aset => 0,
c_sync_enable => 0,
c_enable_rlocs => 0,
c_has_aclr => 0,
c_has_sset => 0,
c_sync_priority => 0,
c_has_ainit => 0,
c_has_sclr => 0
)
PORT MAP (
D => BU198_D,
Q => BU198_Q,
CLK => BU198_CLK,
CE => BU198_CE
);
BU212_CLK <= n36;
n393 <= BU212_SDOUT;
BU212 : C_SHIFT_FD_V7_0
GENERIC MAP (
c_has_aset => 0,
c_has_d => 0,
c_sync_priority => 0,
c_has_sclr => 0,
c_fill_data => 1,
c_width => 2,
c_enable_rlocs => 0,
c_ainit_val => "00",
c_has_ce => 0,
c_has_aclr => 0,
c_sync_enable => 0,
c_has_ainit => 0,
c_has_sdout => 1,
c_sinit_val => "00",
c_has_sset => 0,
c_has_sinit => 0,
c_has_q => 0,
c_shift_type => 1,
c_has_sdin => 0,
c_has_lsb_2_msb => 0
)
PORT MAP (
CLK => BU212_CLK,
SDOUT => BU212_SDOUT
);
END xilinx;
-- synopsys translate_on
------------------------------------------------------------------------
I could implement this quite easily on my S3 kit by wiring up a few
resistors as a simple ladder network DAC and attaching it to one of the
connectors. I've just checked and the standard oscillator is 50 MHz, not 100
MHz.
I should be able to see the output on a scope.
Putting a suitable QSD on a little PCB with an S3, proper DAC and the AF
parts from the SoftRock would make a nice little SDR.
73, Leon
--
Leon Heller, G1HSM
leon.heller at bulldoghome.com
http://www.geocities.com/leon_heller
More information about the Hpsdr
mailing list