[hpsdr] Xilinx Coregen DDS

[Ray Anderson]

KD5NWA wrote:

>Added detail;

>  I agree with Leon that Xilinx does not allow the code to be 
>translated and used on a competitors product. They are very adamant 
>about that point. Xilinx generated code is only for Xilinx parts.




I'm not sure of exactly which license they provide with the s/w shipped
with the demo board, however looking at the COREGEN docs it says:

"If you generate a bitstream and then program an FPGA using a core that
has a Full System Evaluation license, the core will stop working in the
programmed device after 2-8 hours, depending on the core. To get the
device working again you must reload the bitstream (reset or reprogram
the device)." Lovely.....

Hopefully they are providing a time limited full license as opposed to
an Eval license.

If you don't register for the Eval license then the emitted core code
simulates but won't run in a FPGA.


-Ray	WB6TPU




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