[hpsdr] Xilinx Coregen DDS

[Eric Blossom]

On Thu, Jun 15, 2006 at 09:32:07AM +0800, pvharman at arach.net.au wrote:
> Hi Eric,
> 
> No offense taken :).
> 
> In fact Bill KD5TFD and I had exactly this discussion recently. At the moment 
> I'm very much in the 'cobble it together as quickly as possible to see if it 
> works' phase.  As such I tend to use all and any short cuts available. As an 
> example I'm using MatLab to develop the Verilog code for the CIC filter used 
> in Mercury. Also Phil C has written a very nice CORDIC NCO based on the USDR 
> open source code to allow me to get signals from the LT2208 into PowerSDR. 

Understood.

FYI, there's an implementation of a 31-tap halfband that executes in
8-cycles using a single multiplier in the USRP fpga code.
See usrp/fpga/sdr_lib/hb/halfband_decim.v

There's also code for a 4th order CIC with a maximum decimation factor
of 256.  We've been down this path before, and use this code every day ;) 

Eric
K7GNU

 1150335658.0