[hpsdr] Xilinx Coregen DDS

[pvharman at arach.net.au]

Hi Eric,

No offense taken :).

In fact Bill KD5TFD and I had exactly this discussion recently. At the moment 
I'm very much in the 'cobble it together as quickly as possible to see if it 
works' phase.  As such I tend to use all and any short cuts available. As an 
example I'm using MatLab to develop the Verilog code for the CIC filter used 
in Mercury. Also Phil C has written a very nice CORDIC NCO based on the USDR 
open source code to allow me to get signals from the LT2208 into PowerSDR. 

Once this looks like it’s a useful system then I agree we should look at our 
own tools to open the development and maintenance up to as wide a group as 
possible.


Thanks for raising the issue.

73's Phil...VK6APH







> 
> Hi folks,  
> 
> No offense meant to the Xilinx and/or Altera people on the list, but
> given the goals of this group, we'd be better served by ensuring that
> we are not using any vendor supplied code generators.
> 
> Looking at the generated output seems like a reasonable thing to do.
> However, actually using it seems like a step in the wrong direction.
> 
> It wouldn't be a big deal to write some python/lisp/perl/... code that
> given a set of parameters would generate a CORDIC based DDS, or for
> that matter, handle the fixed output frequency in the example.  Once
> the generator was written once, we'd have a piece of free software
> that could be used over and over, independent of the part or tool
> vendor chosen for a particular project.
> 
> Eric
> K7GNU
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