[hpsdr] Horton LO

[Philip Covington]

On 6/16/06, Lyle Johnson <kk7p at wavecable.com> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> In essence, we take the 500 MHz clock, run it to an LVDS transmitter to
> get differential drive (and accept whatever jitter comes from the LVDS
> driver).  We then use a pair of LVPECL D flip-flops to create the
> Johnson Counter.  These are spec'ed at psec levels of jitter.
>
> The four outputs from the counters are then fed through LVDS/LVPECL to
> LVTTL buffers to get our four-phase 125 MHz clock. These feed our FPGA
> clock inputs.
>
> Four outputs from the FPGA drive the QSD sampling switch directly, with
> a 50% duty cycle output (or perhaps some other duty cycle if it is
> better to do so). Or drive multiple QSDs for diversity reception...
>
> For Tx, we can use the same outputs, or add four more programmable
> dividers to drive the sampling switch for the QSE, so we can do full
> duplex on two different frequencies :-)
>
> 73,
>
> Lyle KK7P

Hi Lyle,

Analog Devices has some really great looking LVDS/LVPECL clock
distribution ICs that we could use to get our clocks distributed all
the places we need to.

73 de Phil N8VB

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